1GB-AUTO-AS4C128M8D3 Datasheet, PDF (8/84 Pages) Alliance Semiconductor Corporation – Fully synchronous operation

1Gb Auto-AS4C128M8D3
ODT
RESET#
VDD
VSS
VDDQ
VSSQ
VREFCA
VREFDQ
ZQ
NC
Input
On Die Termination: ODT (registered HIGH) enables termination resistance internal to
the DDR3 SDRAM. When enabled, ODT is applied to each DQ, DQS, DQS#, DM/TDQS
and TDQS# signal. (When TDQS is enabled via Mode Register A11=1 in MR1) The ODT
pin will be ignored if Mode-registers, MR1and MR2, are programmed to disable RTT.
Input
Active Low Asynchronous Reset: Reset is active when RESET# is LOW, and inactive
when RESET# is HIGH. RESET# must be HIGH during normal operation. RESET# is a
CMOS rail to rail signal with DC high and low at 80% and 20% of VDD
Supply Power Supply: +1.5V ±0.075V
Supply Ground
Supply DQ Power: +1.5V ±0.075V.
Supply DQ Ground
Supply Reference voltage for CA
Supply Reference voltage for DQ
Supply Reference pin for ZQ calibration.
- No Connect: These pins should be left unconnected.
Confidential
-8-
Rev.1.0 May 2015