1GB-AUTO-AS4C128M8D3 Datasheet, PDF (48/84 Pages) Alliance Semiconductor Corporation – Fully synchronous operation

1Gb Auto-AS4C128M8D3
Power-Down Modes
l Power-Down Entry and Exit
Power-Down is synchronously entered when CKE is registered low (along with NOP or Deselect command). CKE is
not allowed to go low while mode register set command, MPR operations, ZQCAL operations, DLL locking or
read/write operation are in progress. CKE is allowed to go low while any of other operation such as row activation,
precharge or auto precharge and refresh are in progress, but power-down IDD spec will not be applied until finishing
those operation.
The DLL should be in a locked state when power-down is entered for fastest power-down exit timing. If the DLL is
not locked during power-down entry, the DLL must be reset after exiting power-down mode for proper read
operation and synchronous ODT operation. DRAM design provides all AC and DC timing and voltage specification
as well proper DLL operation with any CKE intensive operations as long as DRAM controller complies with DRAM
specifications.
During Power-Down, if all banks are closed after any in progress commands are completed, the device will be in
precharge Power-Down mode; if any bank is open after in progress commands are completed, the device will be in
active Power-Down mode.
Entering Power-down deactivates the input and output buffers, excluding CK, CK, ODT, CKE, and RESET#.
To protect DRAM internal delay on CKE line to block the input signals, multiple NOP or Deselect commands are
needed during the CKE switch off and cycle(s) after, this timing period are defined as tCPDED. CKE_low will result
in deactivation of command and address receivers after tCPDED has expired.
Table 24. Power-Down Entry Definitions
Status of DRAM
MRS bit A12 DLL
Active
(A Bank or more open)
Don't Care On
Precharged
(All Banks Precharged)
0
Off
Precharged
(All Banks Precharged)
1
On
PD Exit Relevant Parameters
Fast
Slow
Fast
tXP to any valid command.
tXP to any valid command. Since it is in
precharge state, commands here will be ACT,
AR, MRS/EMRS, PR or PRA.
tXPDLL to commands who need DLL to
operate, such as RD, RDA or ODT control line.
tXP to any valid command.
Also the DLL is disabled upon entering precharge power-down (Slow Exit Mode), but the DLL is kept enabled during
precharge power-down (Fast Exit Mode) or active power-down. In power-down mode, CKE low, RESET# high, and
a stable clock signal must be maintained at the inputs of the DD3 SDRAM, and ODT should be in a valid state but
all other input signals are “Don’t care” (If RESET# goes low during Power-Down, the DRAM will be out of PD mode
and into reset state).
CKE low must be maintain until tCKE has been satisfied. Power-down duration is limited by 9 times tREFI of the
device. The power-down state is synchronously exited when CKE is registered high (along with a NOP or Deselect
command).CKE high must be maintained until tCKE has been satisfied. A valid, executable command can be
applied with power-down exit latency, tXP and/or tXPDLL after CKE goes high. Power-down exit latency is defined
at AC spec table of this datasheet.
Confidential
-48-
Rev.1.0 May 2015