1GB-AUTO-AS4C128M8D3 Datasheet, PDF (72/84 Pages) Alliance Semiconductor Corporation – Fully synchronous operation

1Gb Auto-AS4C128M8D3
Figure 52. WRITE(BC4) to WRITE(BC8) OTF
CK#
CK
Notes 3
COMMAND
Notes 4
ADDRESS
DQS, DQS#
Notes 2
DQ
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
WRITE
NOP
Bank
Col n
NOP
NOP
tCCD
WRITE
NOP
Bank
Col b
tWPRE
NOP
NOP
tWPST
NOP
NOP
tWPRE
NOP
NOP
4 Clocks
NOP
NOP
NOP
tWR
tWTR
tWPST
WL = 5
Din
Din
Din
Din
n
n+1
n+2
n+3
NOTES:
1. WL = 5 (CWL = 5, AL = 0)
2. DIN n (or b) = data-in from column n (or column b).
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0[A1:0 = 01] and A12 = 0 during WRITE command at T0.
BL8 setting activated by MR0[A1:0 = 01] and A12 = 1 during WRITE command at T4.
WL = 5
Din
Din
Din
Din
Din
Din
Din
Din
b
b+1
b+2
b+3
b+4
b+5
b+6
b+7
TRANSITIONING DATA
Don't Care
Figure 53. Refresh Command Timing
T0
T1
CK#
CK
Ta0
Ta1
Tb0
Tb1
Tb2
COMMAND
REF
NOP
NOP
REF
NOP
NOP
VALID
VALID
VALID
tRFC
tRFC (min)
tREFI (max. 9 * tREFI)
DRAM must be idle
NOTES:
1. Only NOP/DES commands allowed after Refresh command registered until tRFC(min) expires.
2. Time interval between two Refresh commands may be extended to a maximum of 9 x tREFI.
Tb3
Tc0
Tc1
Tc2
Tc3
VALID
VALID
REF
VALID
VALID
VALID
DRAM must be idle
TIME BREAK
TRANSITIONING DATA
Don't Care
Figure 54. Self-Refresh Entry/Exit Timing
T0
T1
T2
Ta0
CK#
CK
t_CKSRE
CKE
ODT
t_IS t_CPDED
t_IS
ODTL
t_CKESR
COMMAND
NOP
SRE
NOP
ADDR
t_RP
Enter Self
Refresh
NOTES:
1. Only NOP or DES command.
2. Valid commands not requiring a locked DLL.
3. Valid commands requiring a locked DLL.
Tb0
Tc0
Tc1
Td0
Teo
Tf0
t_CKSRX
VALID
VALID
VALID
SRX
Notes 1
NOP
t_XS
Notes 2
VALID
Notes 3
VALID
Exit Self
Refresh
t_XSDLL
VALID
VALID
TIME BREAK
Don't Care
Confidential
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Rev.1.0 May 2015