1GB-AUTO-AS4C128M8D3 Datasheet, PDF (56/84 Pages) Alliance Semiconductor Corporation – Fully synchronous operation

1Gb Auto-AS4C128M8D3
- Slew Rate Definition for Differential Input Signals
Input slew rate for differential signals (CK, CK# and DQS, DQS#) are defined and measured as shown below.
Table 31. Differential Input Slew Rate Definition
Description
Measured
From
To
Defined by
Differential input slew rate for rising edge
VILdiffmax
(CK, CK# and DQS, DQS#)
VIHdiffmin
[VIHdiffmin-VILdiffmax] /
DeltaTRdiff
Differential input slew rate for falling edge
VIHdiffmin
(CK, CK# and DQS, DQS#)
VILdiffmax
[VIHdiffmin-VILdiffmax] /
DeltaTFdiff
NOTE: The differential signal (i.e., CK, CK# and DQS, DQS#) must be linear between these thresholds.
Table 32. Single-ended AC and DC Output Levels
Symbol
Parameter
-12BAN
Unit Note
VOH(DC) DC output high measurement level (for IV curve linearity)
0.8 x V_DDQ
V
VOM(DC) DC output mid measurement level (for IV curve linearity)
0.5 x V_DDQ
V
VOL(DC) DC output low measurement level (for IV curve linearity)
0.2 x V_DDQ
V
VOH(AC) AC output high measurement level (for output SR)
V_TT + 0.1 x V_DDQ
V
1
VOL(AC) AC output low measurement level (for output SR)
V_TT - 0.1 x V_DDQ
V
1
NOTE 1: The swing of ± 0.1 × VDDQ is based on approximately 50% of the static single-ended output high or low swing with
a driver impedance of 40Ω and an effective test load of 25Ω to VTT = VDDQ/2.
Table 33. Differential AC and DC Output Levels
Symbol
Parameter
-12BAN
Unit Note
VOHdiff(AC) AC differential output high measurement level (for output SR)
+ 0.2 x V_DDQ
V1
VOLdiff(AC) AC differential output low measurement level (for output SR)
- 0.2 x V_DDQ
V1
NOTE 1: The swing of ± 0.2 × VDDQ is based on approximately 50% of the static single-ended output high or low swing with
a driver impedance of 40Ω and an effective test load of 25Ω to VTT = VDDQ/2 at each of the differential outputs.
Confidential
-56-
Rev.1.0 May 2015