1GB-AUTO-AS4C128M8D3 Datasheet, PDF(34/84 Page) Alliance Semiconductor Corporation

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1GB-AUTO-AS4C128M8D3 Datasheet, PDF (34/84 Pages) Alliance Semiconductor Corporation – Fully synchronous operation

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1Gb Auto-AS4C128M8D3

lï¬ DLL on/off switching procedure

DDR3 DLL-off mode is entered by setting MR1 bit A0 to â1â; this will disable the DLL for subsequent operation until

A0 bit set back to â0â.

lï¬ DLL âonâ to DLL âoffâ Procedure

To switch from DLL âonâ to DLL âoffâ requires the frequency to be changed during Self-Refresh outlined in the

following procedure:

1. Starting from Idle state (all banks pre-charged, all timing fulfilled, and DRAMs On-die Termination resistors,

RTT, must be in high impedance state before MRS to MR1 to disable the DLL).

2. Set MR1 Bit A0 to â1â to disable the DLL.

3. Wait tMOD.

4. Enter Self Refresh Mode; wait until (tCKSRE) satisfied.

5. Change frequency, in guidance with âInput Clock Frequency Changeâ section.

6. Wait until a stable clock is available for at least (tCKSRX) at DRAM inputs.

7. Starting with the Self Refresh Exit command, CKE must continuously be registered HIGH until all tMOD

timings from any MRS command are satisfied. In addition, if any ODT features were enabled in the mode

registers when Self Refresh mode was entered, the ODT signal must continuously be registered LOW until all

tMOD timings from any MRS command are satisfied. If both ODT features were disabled in the mode

registers when Self Refresh mode was entered, ODT signal can be registered LOW or HIGH.

8. Wait tXS, and then set Mode Registers with appropriate values (especially an update of CL, CWL, and WR

may be necessary. A ZQCL command may also be issued after tXS).

9. Wait for tMOD, and then DRAM is ready for next command.

Figure 10. DLL Switch Sequence from DLL-on to DLL-off

Ta0

Ta1

Tb0

Tc0

Td0

Td1

CK#

CKE

COMMAND

Notes 2

MRS

NOP

Notes 1

tMOD

Notes 3

SRE

NOP

tCKSRE

Notes 4

tCKESR

Notes 6

SRX

NOP

Notes 5

tCKSRX

tXS

ODT

ODT: Static LOW in case RTT_Nom and RTT_WR is enabled, otherwise static Low or High

NOTES:

1. Starting with Idle State, RTT in Hi-Z state

2. Disable DLL by setting MR1 Bit A0 to 1

3. Enter SR

4. Change Frequency

5. Clock must be stable tCKSRX

6. Exit SR

7. Update Mode registers with DLL off parameters setting

8. Any valid command

Te0

Te1

Tf0

Notes 7

MRS

NOP

tMOD

Notes 8

VALID

Notes 8

VALID

Notes 8

VALID

TIME BREAK

Don't Care

Confidential

-34-

Rev.1.0 May 2015

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