1GB-AUTO-AS4C128M8D3 Datasheet, PDF (27/84 Pages) Alliance Semiconductor Corporation – Fully synchronous operation

1Gb Auto-AS4C128M8D3
Table 18. Electrical Characteristics and Recommended A.C. Operating Conditions
(VDD = 1.5V ± 0.075V, T_OPER = -40~105 °C)
Symbol
t_AA
t_RCD
t_RP
t_RC
t_RAS
t_CK(avg)
t_{CK (DLL_OFF)}
t_CH(avg)
t_CL(avg)
t_DQSQ
t_QH
t_LZ(DQ)
t_HZ(DQ)
t_DS(base)
t_DH(base)
t_DIPW
t_RPRE
t_RPST
t_QSH
t_QSL
t_WPRE
t_WPST
t_DQSCK
t_LZ(DQS)
t_HZ(DQS)
t_DQSL
t_DQSH
t_DQSS
t_DSS
t_DSH
t_DLLK
t_RTP
t_WTR
t_WR
t_MRD
t_MOD
t_CCD
Parameter
Internal read command to first data
ACT to internal read or write delay time
PRE command period
ACT to ACT or REF command period
ACTIVE to PRECHARGE command period
CL=7, CWL=6
CL=8, CWL=6
Average clock period
CL=9, CWL=7
CL=10, CWL=7
CL=11, CWL=8
Minimum Clock Cycle Time (DLL off mode)
Average clock HIGH pulse width
Average Clock LOW pulse width
DQS, DQS# to DQ skew, per group, per access
DQ output hold time from DQS, DQS#
DQ low-impedance time from CK, CK#
DQ high impedance time from CK, CK#
Data setup time to DQS, DQS#
referenced to Vih(ac) / Vil(ac) levels
AC150
Data hold time from DQS, DQS#
referenced to Vih(dc) / Vil(dc) levels
DC100
DQ and DM Input pulse width for each input
DQS,DQS# differential READ Preamble
DQS, DQS# differential READ Postamble
DQS, DQS# differential output high time
DQS, DQS# differential output low time
DQS, DQS# differential WRITE Preamble
DQS, DQS# differential WRITE Postamble
DQS, DQS# rising edge output access
time from rising CK, CK#
DQS and DQS# low-impedance time
(Referenced from RL - 1)
DQS and DQS# high-impedance time
(Referenced from RL + BL/2)
DQS, DQS# differential input low pulse width
DQS, DQS# differential input high pulse width
DQS, DQS# rising edge to CK, CK# rising edge
DQS, DQS# falling edge setup time to
CK, CK# rising edge
DQS, DQS# falling edge hold time from
CK, CK# rising edge
DLL locking time
Internal READ Command to
PRECHARGE Command delay
Delay from start of internal write
transaction to internal read command
WRITE recovery time
Mode Register Set command cycle time
Mode Register Set command update delay
CAS# to CAS# command delay
-12BAN
Min. Max.
13.75
20
13.75
-
13.75
-
48.75
-
35
9 * tREFI
1.875
<2.5
1.875
<2.5
1.5
<1.875
1.5
<1.875
1.25
<1. 5
8
-
0.47
0.53
0.47
0.53
-
100
0.38
-
-450
225
-
225
10
-
45
-
360
-
0.9
-
0.3
-
0.4
-
0.4
-
0.9
-
0.3
-
-225
225
-450
225
-
225
0.45
0.55
0.45
0.55
-0.27
0.27
0.18
-
0.18
-
512
-
max (4tCK,
7.5ns)
-
max (4tCK,
7.5ns)
-
15
-
4
-
max
(12tCK,
-
15ns)
4
-
Unit Note
ns
ns
ns
ns
ns
ns ₃₃
ns ₃₃
ns 33
ns ₃₃
ns ₃₃
ns
6
tCK
tCK
ps 13
tCK
13
ps 13,14
ps 13,14
ps 17
ps 17
ps
tCK 13,19
tCK 11,13
tCK
13
tCK
13
tCK
1
tCK
1
ps 13
ps 13, 14
ps 13, 14
tCK 29, 31
tCK 30, 31
tCK
tCK
32
tCK
32
tCK
tCK
tCK
18
ns 18
tCK
tCK
tCK
Confidential
-27-
Rev.1.0 May 2015