1GB-AUTO-AS4C128M8D3 Datasheet, PDF (3/84 Pages) Alliance Semiconductor Corporation – Fully synchronous operation

1Gb Auto-AS4C128M8D3
Overview
The 1Gb Double-Data-Rate-3 DRAMs is double data rate architecture to achieve high-speed operation. It is
internally configured as an eight bank DRAM.
The 1Gb chip is organized as 16Mbit x 8 I/Os x 8 bank devices. These synchronous devices achieve high speed
double-data-rate transfer rates of up to 1600 Mb/sec/pin for general applications.
The chip is designed to comply with all key DDR3 DRAM key features and all of the control and address inputs are
synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential
clocks (CK rising and CK# falling). All I/Os are synchronized with differential DQS pair in a source synchronous
fashion.
These devices operate with a single 1.5V ± 0.075V power supply and are available in BGA packages.
Table . Speed Grade Information
6SHHG*UDGH
Clock Frequency
''5316
80+]
CAS Latency

t_RCD (ns)
13.75
t_RP (ns)
13.75
Table . Ordering Information
Part Number
2UJ
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28M[8
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Package
800
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A: indicates Automotive temperature
N: LQGLFDWHV ROHS compliant 3E)UHHDQG+DORJHQ)UHH
Confidential
-3-
Rev.1.0 May 2015