AK4637EN Datasheet, PDF (91/96 Pages) Asahi Kasei Microsystems – 24bit Mono CODEC with MIC/SPK-AMP

[AK4637]
■ Lineout Output
FS3-0 bits ₁₀₁₁
(Addr:06H, D3-0)
1011
(1)
(12)
LOSEL bit
(Addr:00H, D3)
DACL bit
(2)
(3)
(Addr:04H, D5)
LVCM1-0 bits
XX
01
(Addr:04H, D7-6)
DVOL7-0 bits
(Addr:10H)
18H
(4)
18H
Digital Filter Path
(Addr:18H)
PMDAC bit
(Addr:00H, D2)
PMSL bit
(Addr:01H, D1)
SLPSN bit
(Addr:02H, D7)
AOUT pin
XXH
(5)
(6)
(7)
03H
(11)
(10)
(8)
(9)
>300 ms
>300 ms
Normal Output
Figure 74. Lineout Sequence
Example:
PLL Master Mode
Audio I/F Format: I2S Compatible
Sampling Frequency: 48KHz
Output Digital Volume: 0dB
Line Output Gain: +2dB
Programmable Filter OFF
(1) Addr:06H, Data:0BH
(2) Addr:00H, Data:48H
(3) Addr:04H, Data:60H
(4) Addr:10H, Data:18H
(5) Addr:18H, Data:03H
(6) Addr:00H, Data:4CH
(7) Addr:01H, Data:0EH
(8) Addr:02H, Data:86H
Playback
(9) Addr:02H, Data:06H
(10) Addr:01H, Data:0CH
(11) Addr:00H, Data:48H
(12) Addr:04H, Data:40H
Addr:00H, Data:40H
<Sequence>
At first, clocks must be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS3-0 bits). When the AK4637 is in PLL mode, DAC and Lineout
Output of (6) must be powered-up in consideration of PLL lock time after a sampling frequency
is changed.
(2) Enter Lineout Output Mode: LOSEL bit = “0”  “1” (Addr = 00H)
(3) Set up the path of DAC  Lineout, and Lineout gain setting:
DACL bit = “0”  “1”, LVCM1-0 bits = “xx”  “01” (Addr = 04H)
(4) Set up the output digital volume. (Addr = 10H)
(5) Set up Programmable Filter Path: PFDAC1-0 bit=“00”, PFSDO=ADCPF bits = “1” (Addr = 18H)
(6) Power up DAC: PMDAC bit = “0”  “1” (Addr = 00H)
(7) Power up Lineout Output: PMSL bit = “0”  “1” (Addr =01H)
The AOUT pin starts rising after PMSL bit = “1”. The maximum rise-up time to 99% VCOM
voltage is 300ms when C = 1F and R_L=10k.
(8) Exit the power-save mode of Lineout Output: SLPSN bit = “0”  “1” (Addr = 04H)
SLPSN bit should be set after the AOUT pin is risen up. The AOUT pin starts to output
sound data after SLPSN bit = “0”  “1”.
(9) Enter Lineout Output Power Save Mode: SLPSN bit = “1”  “0” (Addr = 04H)
(10) Power down Lineout Output: PMSL bit = “1”  “0” (Addr = 01H)
(11) Power down DAC: PMDAC bit = “1”  “0” (Addr = 00H)
The AOUT pin is powered down after PMSL bit = “0”. The maximum power down time to 1%
VCOM voltage is 300ms.
(12) Exit the path of DAC  Lineout: DACL bit = “1”  “0” (Addr = 04H)
Exit Lineout Output Mode: LOSEL bit = “1”  “0” (Addr = 00H)
DACL and LOSEL bits should be set after the AOUT pin is powered down.
015010680-E-00
- 91 -
2015/09