AK4637EN Datasheet, PDF (85/96 Pages) Asahi Kasei Microsystems – 24bit Mono CODEC with MIC/SPK-AMP

2. PLL Slave Mode (BICK pin)
[AK4637]
Power Supply
PDN pin
PMVCM bit
(Addr:00H, D6)
PMPLL bit
(Addr:01H, D2)
FCK pin
BICK pin
Internal Clock
(1)
(2) (3)
>2.0ms
(4)
Input
2m (max)
(5)
Example:
Audio I/F Format : I2S Compatible (ADC & DAC)
PLL Reference clock: BICK
BICK frequency: 64fs
Sampling Frequency: 48kHz
(1) Power Supply & PDN pin = “L”  “H”
(2) Dummy Command
Addr:05H, Data:30H
Addr:06H, Data:0BH
Addr:07H, Data:03H
(3) Addr:00H, Data:40H
(4) Addr:01H, Data:04H
Figure 67. Clock Set Up Sequence (2)
<Sequence>
(1) After Power Up: PDN pin “L” → “H”
“L” time of 200ns or more is needed to reset the AK4637.
(2) After Dummy Command (Addr:00H, Data:00H) input, DIF1-0, PLL3-0, and FS3-0 bits must be
set during this period.
(3) Power Up VCOM and Regulator: PMVCM bit = “0” → “1”
VCOM and Regulator must first be powered-up before the other block operates. Power up time
is 2.0ms (max) when the capacitance of an external capacitor for the VCOM is 2.2μF (AVDD ≤
3.6V), 4.7μF(AVDD > 3.6V) and the REGFIL pin is 2.2μF.
(4) PLL starts after the PMPLL bit changes from “0” to “1” and PLL reference clock (BICK pin) is
supplied. PLL lock time is 2ms (max) when BICK is a PLL reference clock.
(5) Normal operation starts after that the PLL is locked.
015010680-E-00
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2015/09