AK4637EN Datasheet, PDF (20/96 Pages) Asahi Kasei Microsystems – 24bit Mono CODEC with MIC/SPK-AMP

■ Timing Diagram
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fs
FCK
tFCKH
tFCKL
1/fBCK
50%TVDD
Duty = tFCKH x fs x 100
tFCKL x fs x 100
BICK
50%TVDD
tBCKH
tBCKL
Duty = tBCKH x fBCK x 100
tBCKL x fBCK x 100
Figure 3. Clock Timing (PLL/EXT Master mode)
[AK4637]
FCK
tFCKH
tDBF
50%TVDD
BICK
(BCKP = "0")
50%TVDD
BICK
(BCKP = "1")
tBSD
50%TVDD
SDTO
tSDS
MSB
tSDH
50%TVDD
VIH
SDTI
VIL
Figure 4. Audio Interface Timing (PLL/EXT Master mode, DSP mode, MSBS bit= “0”)
015010680-E-00
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2015/09