AK4637EN Datasheet, PDF (28/96 Pages) Asahi Kasei Microsystems – 24bit Mono CODEC with MIC/SPK-AMP

[AK4637]
■ PLL Mode
When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) circuit generates a clock that is
selected by PLL3-0 and FS3-0 bits. The PLL lock times, when the AK4637 is supplied stable clocks after
PLL is powered-up (PMPLL bit = “0” → “1”) or the sampling frequency is changed, are shown in Table 5.
Mode
1
2
3
4
5
6
7
12
13
Others
PLL3 PLL2 PLL1 PLL0 PLL Reference
Input
PLL Lock Time
bit bit bit bit Clock Input Pin Frequency
(max)
0
0
0
1
BICK pin
16fs
2ms
0
0
1
0
BICK pin
32fs
2ms
0
0
1
1
BICK pin
64fs
2ms
0
1
0
0
MCKI pin 11.2896MHz
5ms
0
1
0
1
MCKI pin
12.288MHz
5ms
0
1
1
0
MCKI pin
12MHz
5ms
0
1
1
1
MCKI pin
24MHz
5ms
1
1
0
0
MCKI pin
13.5MHz
5ms
1
1
0
1
MCKI pin
27MHz
5ms
Others
N/A
Table 5. PLL Mode Setting (*fs: Sampling Frequency, N/A: Not Available)
(default)
■ PLL Unlock State
In this mode, FCK and BICK pins go to “L” until the PLL goes to lock state after PMPLL bit = “0” → “1”
(Table 6).
After the PLL is locked, a first period of FCK and BICK may be invalid clock, but these clocks return to
normal state after a period of 1/fs.
The BICK and FCK pins do not output invalid clocks such as PLL unlock state by setting PMPLL bit to “0”.
During PMPLL bit = “0”, these pins output the same clock as EXT master mode.
PLL State
BICK pin
FCK pin
After PMPLL bit “0” → “1”
“L” Output
“L” Output
PLL Unlock (except the case above)
Invalid
Invalid
PLL Lock
Table 9
1fs Output
Table 6. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
015010680-E-00
- 28 -
2015/09