AK4637EN Datasheet, PDF (19/96 Pages) Asahi Kasei Microsystems – 24bit Mono CODEC with MIC/SPK-AMP

[AK4637]
Parameter
Control Interface Timing (I²C Bus) (Note 24)
Symbol Min. Typ. Max. Unit
SCL Clock Frequency
fSCL
-
-
400 kHz
Bus Free Time Between Transmissions
tBUF 1.3
-
-
s
Start Condition Hold Time (prior to first clock pulse)
tHD:STA 0.6
-
-
s
Clock Low Time
tLOW 1.3
-
-
s
Clock High Time
tHIGH 0.6
-
-
s
Setup Time for Repeated Start Condition
tSU:STA 0.6
-
-
s
SDA Hold Time from SCL Falling (Note 25)
tHD:DAT 0
-
-
s
SDA Setup Time from SCL Rising
tSU:DAT 0.1
-
-
s
Rise Time of Both SDA and SCL Lines
tR
-
-
0.3 s
Fall Time of Both SDA and SCL Lines
tF
-
-
0.3 s
Setup Time for Stop Condition
tSU:STO 0.6
-
-
s
Capacitive Load on Bus
Cb
-
-
400 pF
Pulse Width of Spike Noise Suppressed by Input Filter
tSP
0
-
50 ns
Power-down & Reset Timing
PDN Accept Pulse Width
(Note 26)
tAPD 200
-
-
ns
PDN Reject Pulse Width
(Note 26)
tRPD
-
-
50 ns
PMADC “” to SDTO valid
(Note 27)
ADRST1-0 bits =“00”
tPDV
- 1059 - 1/fs
ADRST1-0 bits =“01”
tPDV
-
267
- 1/fs
ADRST1-0 bits =“10”
tPDV
-
531
- 1/fs
ADRST1-0 bits =“11”
tPDV
-
135
- 1/fs
VCOM Voltage
Rising Time
(Note 28)
Note 24. I²C Bus is a trademark of NXP B.V.
tRVCM
-
0.6 2.0 ms
Note 25. Data must be held for sufficient time to bridge the 300ns transition time of SCL.
Note 26. The AK4637 can be reset by the PDN pin = “L”. The PDN pin must be held “L” for more than
200ns for a certain reset. The AK4637 is not reset by the “L” pulse less than 50ns.
Note 27. This is the count of FCK “↑” from the PMADC bit = “1”.
Note 28. All analog blocks including PLL block are powered up after the VCOM voltage (VCOM pin) rises
up. An external capacitor of the VCOM pin is 2.2μF (AVDD ≤ 3.6V) or 4.7μF (AVDD > 3.6V) and
the REGFIL pin is 2.2F. The capacitance variation should be ±10%.
015010680-E-00
- 19 -
2015/09