AK4637EN Datasheet, PDF (34/96 Pages) Asahi Kasei Microsystems – 24bit Mono CODEC with MIC/SPK-AMP

[AK4637]
■ System Reset
Upon power-up, the AK4637 must be reset by bringing the PDN pin = “L”. This reset is released when a
dummy command is input after the PDN pin = “H”. This ensures that all internal registers reset to their
initial value. Dummy command is executed by writing all “0” to the register address 00H (Figure 25). It is
recommended to set the PDN pin to “L” before power up the AK4637.
In I²C Bus mode, the AK4637 does not return an ACK after receiving a slave address by a dummy
command as shown in Figure 25. In the actual case, initialization cycle starts by 8 SCL clocks during the
PDN pin = “H” regardless of the SDA line. Therefore, retry command is not required (Figure 26).
Executing a write or read command to the other device that is connected to the same I²C Bus also resets
the AK4637.
S
T
A
R/W ="0"
R
T
S
T
O
P
Slave
SDA ^S Address
N ^Sub
N
A Address(00H) A
Data(00H)
N
A
P
C
C
C
K
K
K
Figure 25. Dummy Command in I²C Bus Mode
S
T
A
R/W ="0"
S
T
R
O
T
P
Slave
SDA ^S Address
NP
A
C
K
Figure 26. Reset Completion for example
The ADC starts an initialization cycle by setting PMADC bit to “1” from “0”. The initialization cycle is set by
ADRST1-0 bits (Table 18). During the initialization cycle, the ADC digital data outputs of both channels
are forced to “0” in 2's complement. The ADC output reflects the analog input signal after the initialization
cycle is finished. When using a digital microphone (PMDML/R bits =“0” → “1”), the initialization cycle is
the same as ADC’s.
Note 32. The initial data of ADC has offset data that depends on microphones and the cut-off frequency of
HPF. If this offset is not small, make initialization cycle longer by setting ADRST1-0 bits or do not
use the first data of ADC outputs.
ADRST1-0 bits
00
01
10
11
Initialize Cycle
Cycle
fs = 8kHz
fs = 16kHz
1059/fs
132.4ms
66.2ms
267/fs
33.4ms
16.7ms
531/fs
66.4ms
33.2ms
135/fs
16.9ms
8.4ms
Table 18. ADC Initialization Cycle
fs = 48kHz
22ms
5.6ms
11.1ms
2.8ms
(default)
The DAC is initialized by setting PMDAC bit “0” → “1”. The initialization cycle is 2/fs. Therefore, the DAC
outputs signals after group delay period and 2/fs when power up the device. Normally, this group delay
period or 2/fs initialization cycle mentioned above is absorbed by power-up time of amplifiers after the
DAC (Lineout-amp, SPK-amp).
015010680-E-00
- 34 -
2015/09