AK4637EN Datasheet, PDF (60/96 Pages) Asahi Kasei Microsystems – 24bit Mono CODEC with MIC/SPK-AMP

[AK4637]
■ Speaker Output (SPP/SPN pins, LOSEL bit = “0”)
When LOSEL bit = “0”, the DAC output signal is input to the speaker amplifier. The speaker amplifier has
mono output as it is BTL capable. The gain and output level are set by SPKG1-0 bits. The output level
depends on AVDD and SPKG1-0 bits setting.
SPKG1-0 bits
Gain
SPK-Amp Output Level
(DAC Input =0dBFS, AVDD=3.3V)
00
+6.4dB
3.36Vpp
(default)
01
+8.4dB
4.23Vpp (Note 37)
10
+11.1dB
5.76Vpp (Note 37)
11
+14.9dB
8.90Vpp (AVDD=5.0V; Note 37)
Note 37. The output level is calculated on the assumption that the signal is not clipped. However, in the
actual case, the SPK-Amp output signal is clipped when DAC outputs 0dBFS signal. The
SPK-Amp output level should be kept under 4.0Vpp (AVDD=3.3V) by adjusting digital volume to
prevent clipped noise.
Table 47. SPK-Amp Gain
< Speaker-Amp Control Sequence >
The speaker amplifier is powered-up/down by PMSL bit. When PMSL bit is “0” at LOSEL bit = “0”, SPP
pin is pulled-down to VSS1 by 100kΩ (typ) and the SPN pin is placed in a Hi-Z state. When PMSL bit is “1”
and SLPSN bit is “0” at LOSEL bit = “0”, the speaker amplifier enters power-save mode. In this mode, the
SPP pin is placed in Hi-Z state and the SPN pin outputs AVDD/2 voltage.
When the PMSL bit is “1” at LOSEL bit = “0” after the PDN pin is changed from “L” to “H”, the SPP and
SPN pins rise up in power-save mode. In this mode, the SPP pin is placed in a Hi-Z state and the SPN pin
goes to AVDD/2 voltage. Because the SPP and SPN pins rise up in power-save mode, pop noise can be
reduced. When the AK4637 is powered-down (PMSL bit = “0”), pop noise can also be reduced by first
entering power-save-mode.
PMSL
bit
0
1
SLPSN
bit
x
0
1
Mode
SPP pin
SPN pin
Power-down
Pull-down to VSS1
Hi-Z
Power-save
Hi-Z
AVDD/2
Normal Operation Normal Operation Normal Operation
Table 48 Speaker-Amp Mode Setting (x: Don’t care)
(default)
LOSEL bit Don't care
"L"
PMSL bit
SLPSN bit
>1ms
>0ms
SPP pin
Hi-Z
Hi-Z
SPN pin
AVDD/2
Hi-Z
AVDD/2
Hi-Z
Figure 50. Power-up/Power-down Timing for Speaker-Amp
015010680-E-00
- 60 -
2015/09