AK4380 Datasheet, PDF (9/21 Pages) Asahi Kasei Microsystems – 100dB 24BIT 96kHz 2CH DAC

ASAHI KASEI
[AK4380]
OPERATION OVERVIEW
n System Clock
The external clocks, which are required to operate the AK4380, are MCLK, LRCK and BICK. The master clock (MCLK)
corresponds to 256fs, 384fs, 512fs or 768fs (for normal speed mode; 128fs, 192fs, 256fs or 384fs for double speed mode).
MCLK frequency is automatically detected, and the internal master clock becomes 256fs (for normal speed mode; 128fs
for double speed mode). The MCLK should be synchronized with LRCK but the phase is not critical. Table 1∼3 illustrate
corresponding clock frequencies.
All external clocks (MCLK, BICK and LRCK) should always be present whenever the AK4380 is in the normal operation
mode (PDN= “H”). If these clocks are not provided, the AK4380 may draw excess current because the device utilizes
dynamic refreshed logic internally. The AK4380 should be reset by PDN= “L” after threse clocks are provided. If the
external clocks are not present, the AK4380 should be in the power-down mode (PDN= “L”). After exiting reset at
power-up etc., the AK4380 is in the power-down mode until MCLK and LRCK are input.
DFS pin / DFS bit
LRCK Frequency (fs)
MCLK Frequency
Normal Speed Mode
“L” / “0”
8kHz~48kHz
256fs,384fs,512fs,768fs
Double Speed Mode
“H” / “1”
8kHz~96kHz
128fs,192fs,256fs,384fs
Table 1. System clock
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
256fs
8.1920MHz
11.2896MHz
12.2880MHz
MCLK
384fs
512fs
12.2880MHz 16.3840MHz
16.9344MHz 22.5792MHz
18.4320MHz 24.5760MHz
768fs
24.5760MHz
33.8688MHz
36.8640MHz
BICK
64fs
2.0480MHz
2.8224MHz
3.0720MHz
Table 2. System clock example (Normal Speed Mode)
LRCK
fs
88.2kHz
96.0kHz
128fs
11.2896MHz
12.2880MHz
MCLK
192fs
256fs
16.9344MHz 22.5792MHz
18.4320MHz 24.5760MHz
384fs
33.8688MHz
36.8640MHz
BICK
64fs
5.6448MHz
6.1440MHz
Table 3. System clock example (Double Speed Mode)
MS0018-E-01
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