AK4380 Datasheet, PDF (18/21 Pages) Asahi Kasei Microsystems – 100dB 24BIT 96kHz 2CH DAC

ASAHI KASEI
[AK4380]
SYSTEM DESIGN
Figure 9 and 10 show the system connection diagram. An evaluation board (AKD4380) is available in order to allow an
easy study on the layout of a surrounding circuit.
Analog 5V
Master Clock
64fs
24bit Audio Data
fs
Reset & Power down
Mode
Setting
System Ground
1 MCLK
DZF 16
2 BICK
VREF 15
3 SDTI
4 LRCK
AK4380
VDD 14
VSS 13
5 PDN
VCOM 12
6 SMUTE
AOUTL 11
7 DFS
AOUTR 10
8 DIF0
P/S 9
Analog Ground
Optional External
Mute Circuits
0.1u ⁺ 10u
10u
+
+
10u
220
27k
+
10u
220
27k
Lch Out
Rch Out
Figure 9. Typical Connection Diagram (Parallel mode)
Analog 5V
Master Clock
64fs
24bit Audio Data
fs
Reset & Power down
Micro-
Controller
System Ground
1 MCLK
2 BICK
3 SDTI
4 LRCK
5 PDN
6 CSN
7 CCLK
8 CDTI
AK4380
DZF 16
VREF 15
VDD 14
VSS 13
VCOM 12
AOUTL 11
AOUTR 10
P/S 9
Analog Ground
Optional External
Mute Circuits
0.1u ⁺ 10u
10u
+
+
10u
220
27k
+
10u
220
27k
Lch Out
Rch Out
Figure 10. Typical Connection Diagram (Serial mode)
Notes:
- When AOUT drives some capacitive load, some resistor should be added in series between AOUT and the load.
- ALL input pins except internal pull-up pin should not be left floating.
- Decoupling capacitor, especially 0.1µF ceramic capacitor for high frequency should be placed as near to VDD and
VREF pins as possible.
- System ground including DSP/µP should be separated from AK4380’s VSS. Both grounds should be connected by one
point at power supply or regulator on system board.
MS0018-E-01
- 18 -
2000/8