AK4380 Datasheet, PDF (2/21 Pages) Asahi Kasei Microsystems – 100dB 24BIT 96kHz 2CH DAC

ASAHI KASEI
[AK4380]
n Ordering Guide
AK4380VT
AKD4380
-40 ∼ +85°C
16pin TSSOP (0.65mm pitch)
Evaluation Board for AK4380
n Pin Layout
MCLK
1
16
DZF
BICK
2
15
VREF
SDTI
3
14
VDD
LRCK
4
PDN
5
SMUTE/CSN
6
Top
View
13
VSS
12
VCOM
11
AOUTL
DFS/CCLK
7
DIF0/CDTI
8
10
AOUTR
9
P/S
PIN/FUNCTION
No. Pin Name
I/O Function
1 MCLK
I Master Clock Input Pin
An external TTL clock should be input on this pin.
2 BICK
I Audio Serial Data Clock Pin
3 SDTI
I Audio Serial Data Input Pin
4 LRCK
I L/R Clock Pin
5 PDN
I Power-Down Mode Pin
When at “L”, the AK4380 is in the power-down mode and is held in reset.
The AK4380 should always be reset upon power-up.
6 SMUTE
I Soft Mute Pin in parallel mode
“H”: Enable, “L”: Disable
CSN
I Chip Select Pin in serial mode
7 DFS
I Double Speed Sampling Mode Pin in parallel mode
“L”: Normal Speed, “H”: Double Speed
CCLK
I Control Data Input Pin in serial mode
8 DIF0
I Audio Data Interface Format Pin in parallel mode
CDTI
I Control Data Input Pin in serial mode
9 P/S
I
Parallel/Serial Select Pin
(Internal pull-up pin)
“L”: Serial control mode, “H”: Parallel control mode
10 AOUTR
O Rch Analog Output Pin
11 AOUTL
O Lch Analog Output Pin
12 VCOM
O Common Voltage Pin, VDD/2
Normally connected to VSS with a 0.1µF ceramic capacitor in parallel with
a 10µF electrolytic cap.
13 VSS
- Ground Pin
14 VDD
- Power Supply Pin
15 VREF
I Voltage Reference Input Pin
16 DZF
O Data Zero Input Detect Pin
When SDTI of both channels follow a total 8192 LRCK cycles with “0” input
data, this spin goes to “H”.
Note: All input pins except pull-up pin should not be left floating.
MS0018-E-01
-2-
2000/8