AK4380 Datasheet, PDF (14/21 Pages) Asahi Kasei Microsystems – 100dB 24BIT 96kHz 2CH DAC

ASAHI KASEI
[AK4380]
n System Reset
The AK4380 should be reset once by bringing PDN = “L” upon power-up. The AK4380 is powered up and the internal
timing starts clocking by LRCK “↑” after exiting reset and power down state by MCLK. The AK4380 is in the power-down
mode until MCLK and LRCK are input.
n Power-down
The AK4380 is placed in the power-down mode by bringing PDN pin “L” and the anlog outputs are floating (Hi-Z). Figure
6 shows an example of the system timing at the power-down and power-up.
PDN
Internal
State
D/A In
(Digital)
D/A Out
(Analog)
Clock In
MCLK, LRCK, BICK
DZF
Normal Operation
Power-down
“0” data
GD (1)
(3) (2)
(4)
Don’t care
(6)
Normal Operation
GD (1)
(3)
External
MUTE
(5)
Mute ON
Notes:
(1) The analog output corresponding to the digital input has a group delay, GD.
(2) Analog outputs are floating (Hi-Z) at the power-down mode.
(3) Click noise occures at the edges(“↑ ↓”) of PDN signal. This noise is output even if input data is “0”.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the power-down mode (PDN = “L”).
(5) Please mute the analog output externally if the click noise(3) influences system application. The timing example is
shown in this figure.
(6) DZF pin is “L” in the power-down mode (PDN = “L”).
Figure 6. Power-down/up sequence example
MS0018-E-01
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