AK4380 Datasheet, PDF (16/21 Pages) Asahi Kasei Microsystems – 100dB 24BIT 96kHz 2CH DAC

ASAHI KASEI
[AK4380]
n Mode Control Interface
Some function of AK4380 can be controlled by pins (parallel control mode) shown in Table 6. The serial control interface
is enabled by the P/S pin = “L”. Internal registers may be written by 3-wire µP interface pins: CSN, CCLK and CDTI. The
data on this interface consists of Chip Address (2bits, CAD1/0; fixed to “01”), Read/Write (1bit; fixed to “1”, Write only),
Register Address (MSB first, 5bits) and Control Data (MSB first, 8bits). AK4380 latches the data on the rising edge of
CCLK, so data should clocked in on the falling edge. The writing of data becomes valid by CSN “↑”. The clock speed of
CCLK is 5MHz (max). The CSN and CCLK must be fixed to “H” when the register does not be accessed.
Function
Double speed
De-emphasis
SMUTE
Zero Detection
16/20/24bit LSB justified format
Parallel mode
O
X
O
O
X
Serial mode
O
O
O
O
O
Table 7. Function list (O: available, X: not available)
PDN = “L” resets the registers to their default values. When the state of P/S pin is changed, AK4380 should be reset by
PDN= “L”. In the serial mode, the internal timing circuit is reset by RSTN bit, but the registers are not initialized.
CSN
CCLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0:
R/W:
A4-A0:
D7-D0:
Chip Address (Fixed to “01”)
READ/WRITE (Fixed to “1”, Write only)
Register Address
Control Data
Figure 8. Control I/F Timing
* The AK4380 does not support the read command and chip address. C1, C0 and R/W are fixed to “011”
* When the AK4380 is in the power down mode (PDN = “L”) or the MCLK is not provided, writing into the control
register is inhibited.
MS0018-E-01
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