AK8855 Datasheet, PDF (70/81 Pages) Asahi Kasei Microsystems – NTSC/PAL Digital Video Decoder

[ASAHI KASEI]
PGA Control Register (R/W) [Sub Address 0x05]
Register to set gain of PGA.
When AGC function is enabled, gain value set by AGC is set to this register.
AK8855
Sub Address 0x05
bit 7
bit 6
Reserved
PGA6
0
1
bit 5
PGA5
0
bit 4
bit 3
PGA4
PGA3
Default Value
0
0
bit 2
PGA2
1
Default Value: 0x46
bit 1
bit 0
PGA1
PGA0
1
0
PGA Control Register Definition
BIT
Register
Name
bit 0
PGA0
~
~
PGA Gain Set
bit 6
PGA6
bit 7 Reserved
Reserved
R/
W
Definition
R/
W
to set gain of PGA.
PGA can be adjusted in approximately 0.1 dB /
step.
R/
W
Reserved
Note ) when to read this register while AGC is enabled, the PGA value which is set by AGC is returned.
It is possible to write value by user ( user-set-value ) while AGC is enabled, but its value is not written to PGA.
A returned value made by register read operation also becomes above mentioned AGC set-value.
When AGC is disabled, user-set-value is valid, and its value ( user-set-value ) is returned by Register Read
operation.
MS0319-E-03
70
2004 / 11