AK8855 Datasheet, PDF (7/81 Pages) Asahi Kasei Microsystems – NTSC/PAL Digital Video Decoder

[ASAHI KASEI]
(4) AC Characteristics
Parameter
Digital output maximum
allowable load capacitance
AK8855
Symbol Min
Typ
Max Units
Conditions
CL
15
pF PVDD =1.6~2.0V
30
pF PVDD = 2.7~3.3V
(5) Analog Characteristics < AVDD = 3.0 V, temperature 25 °C >
Selector Clamp
Parameter
Symbol Min
Typ
Maximum input range
VIMX
Clamp level
VYCP
0.9
Clamp current
CLPI
150
Max
1
Units
V_PP
V
uA
Conditions
PGA
Parameter
Resolution
Minimum gain
Maximum gain
Gain step
Symbol Min
GMN
GMX
GST
Typ
7
0
12
0.094
Max
Units
bit
dB
dB
dB
Conditions
AD Converter
Parameter
Resolution
operating clock frequency
Integral non-linearity error
Differential non-linearity error
S/N
S/(N+D)
ADC internal common voltage
ADC ADC internal
positive-side VREF voltage
ADC internal
negative-side VREF voltage
Symbol Min
RES
FS
INL
DNL
SN
SND
VCOM
VRP
VRN
Typ
10
24.5454
27
2.0
1.0
54
51
1.3
1.7
0.9
Max
4.0
2.0
Units
bits
MHz
LSB
LSB
dB
dB
V
V
Conditions
fs = 27MHz
fs = 27MHz
fin = 1MHz
Ain = -1dB
fs = 27MHz
fin = 1MHz
Ain = -1dB
fs = 27MHz
V
(6) Current consumption < DVDD = AVDD = PVDD = 3.0 V, Ta = -30 ~ +85°C >
Parameter
Symb
ol
Min
Typ
Max Units
Conditions
Operating power supply current
note1)
Total
66
86
mA When an external clock source
is input
Analog part power supply ( AVDD )
Idda
24
mA
Digital part power supply ( DVDD)
Iddd
28
mA When an external clock source
is input
(30)
mA (when a crystal resonator is
connected)
Interface part power supply ( PVDD ) ^Iddp
14
mA CL = 30pF
Power-down current
Total power-down current
1
100 uA
Analog part power supply ( AVDD )
Digital part power supply ( DVDD )
Interface part power supply ( PVDD )
≦1
uA
uA
≦1
uA note2),note3)
≦1
note 1 ) when to decode color bar signal during 601 output mode ( internal system clock at 27 MHz operation ).
note 2 ) output bus potential of data output pin is fixed at PVDD when to measure power-down current. Input
level of digital input pins ( PDN, RSTN, OE ) and input level of I2C pins ( SCLK, SDA ) are fixed to either PVSS
or PVDD.
note 3 ) set digital output pins to PVDD potential, or set OE pin high in power-down setting mode.
MS0319-E-03
7
2004 / 11