AK8855 Datasheet, PDF (19/81 Pages) Asahi Kasei Microsystems – NTSC/PAL Digital Video Decoder

[ASAHI KASEI]
Clock
AK8855
Sampling is done by a fixed clock in the AK8855. PLL to synchronize with Analog input signal is not built-in.
Clock rate differs depending on the selected output picture sizes and types of input signal.
Internal operating clock is either 24.5454 MHz input clock or 27 MHz which is generated from input clock by PLL.
Internal clock to be used is automatically selected by setting output picture size.
operation clock Size
Signal
Note
VGA
24.5454MHz 640 x 480 NTSC/PAL
Interlace output
QVGA
24.5454MHz 320 x 240 NTSC/PAL
Progressive output
CIF
27MHz
352 x 288 NTSC/PAL
Progressive output
QCIF
27MHz
176 x 144 NTSC/PAL
Progressive output
601
27MHz
27MHz
720 x 480
720 x 576
NTSC
PAL
Interlace output
Interlace output
Rotated
QVGA
24.5454MHz 240 x 180 NTSC/PAL
Progressive output
Rotated CIF 24.5454MHz 288 x 216 NTSC/PAL
Progressive output
note ) In case of the rotated CIF size, both left-end and right-end 16 pixels are omitted and 288 X 216 picture size
is output ( 90% area of the effective picture is output ).
When decoding CIF ( NTSC ), output rate is 2X speed of input HD.
Output Picture Size
Setting of output picture size is done by [ OFORM2 : OFORM0 ]-bit of Output Control 1 Register ( R/W )
[ Sub Address 0x01 ]. Setting is as follows.
[OFORM2:OFORM0]-bit
[OFORM2:OFROM0]-bit
000
001
010
011
100
101
110
Function
QVGA
VGA
CIF
QCIF
Rotated QVGA
Rotated CIF
601
Condition
Decimation Filter
Characteristic of Decimation Filter is shown as follows ( shown below is a characteristic at 27 MHz sampling ).
Frequency [MHz]
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0
10.0
0.0
-10.0
-20.0
-30.0
-40.0
-50.0
-60.0
MS0319-E-03
19
2004 / 11