AK8855 Datasheet, PDF (39/81 Pages) Asahi Kasei Microsystems – NTSC/PAL Digital Video Decoder

[ASAHI KASEI]
Timing Chart (Camera I/F)
HV _H
VAF L
DVALID _H
CLKO
(13.5MHz)
D[7:0]
Cb0
CIF (PAL)
Y0
Register Set : VLF = 1’b1, OFORM[2:0] = 3’b010, OIF[1:0] = 2’b00
Cb175
Y350
704 clock @CLKO
Cr175
Y351
0x80
AK8855
0x80
Timing Chart (Camera I/F)
HV _H
VAF L
DVALID _H
CLKO
(6.75MHz)
D[7:0]
Cb0
HD _H
CLKO
(6.75MHz)
QCIF (PAL)
Register Set : VLF = 1’b1, OFORM[2:0] = 3’b011, OIF[1:0] = 2’b00
Y0
Cb87
Y174
Cr87
Y175
0x80
0x80
352 clock @CLKO
In case of QCIF, there is a possibility that the Low period of CLKO signal just before the HV falling edge
becomes 1.5 longer than usual case as left chart.
Even in this case, falling edge of HV and falling edge of CLKO is same timing.
MS0319-E-03
39
2004 / 11