AK8855 Datasheet, PDF (59/81 Pages) Asahi Kasei Microsystems – NTSC/PAL Digital Video Decoder

[ASAHI KASEI]
AK8855
(3) 656 Interface
Since synchronization with input by PLL is not made in 656 Interface mode, those specifications as [ 858
samples / Line, 525 Lines / Frame ] and [ 864 samples / Line, 625 Lines / Frame ] are not strictly satisfied which
are specified by ITU-R BT.656.
Picture data is defined based on HSYNC, and SAV is specified.
In 656 Interface mode, HD / VD / DVALID signals are fixed to low.
HD / VD signals can be output by register setting.
Note )Relation between above mentioned various interface modes and their output format-related registers is
summarized below.
Related registers are [ OFORM1 : OFORM0 ]-bits and [ OIF2 : OIF0 ]-bits of Output Control 1 Register ( R/W )
[ Sub Address 0x01 ].
[OIF1:OIF0]-bit
I/F mode
[OFORM2:OFORM0]-bit
110(601output mode)
Except 110 set
00
Camera I/F mode
O
O
01
Camera I/F mode
(with SAV/EAV)
Not permited
O
10
HD/VD/DVALID I/F
O
O
11
Rec.656
O
Not permited
When items which are impossible to be set are selected, SAV / EAV codes are not guaranteed.
By setting [ TRSVSEL ]-bit of Output Control 1 Register ( R/W ) [ Sub Address 0x01 ], it is possible to
change V-bit shift point of the 656 specified Video Timing Reference code ( SAV / EAV ), separately from the
above
values.
By properly setting [ TRSVSEL ]-bit, it is possible to make the shift point of V-bit compatible with ITU-R
BT.656-3
or ITU-R BT.656-4 & SMPTE125M.
Bit allocation of Output Control 1 Register is as follows.
Sub Address 0x01
bit 7
bit 6
bit 5
bit 4
bit 3
VDPSUP TRSVSEL
OIF1
OIF0
LIMIT601
Default Value
0
0
0
0
0
bit 2
OFORM2
0
Default Value : 0x00
bit 1
bit 0
OFORM1 OFORM0
0
0
[ TRSVSEL ]-bit
TRSVSEL-bit is a control bit to specify V-bit handling within Rec 656 EAV / SAV code.
< V-bit value in Rec. 656 TRS signal and Line relation >
NTSC(525Lines)
PAL(625Lines)
V-bit
TRSVSEL=0
Based on ITU-R
Bt.656-3
TRSVSEL=1
Based on ITU-R
Bt.656-4 and
SMPTE125M
TRSVSEL=0
TRSVSEL=1
V-bit = 0
Line10 ~ Line263
Line273 ~ Line525
Line20 ~ Line263
Line283 ~ Line525
Line23 ~ Line310
Line336 ~ Line623
V-bit = 1
Line1 ~ Line9
Line264 ~ Line272
Line1 ~ Line19
Line264 ~ Line282
Line1 ~ Line22
Line311 ~ Line335
Line624 ~ Line625
(4) About Field Signal Output
The AK8855 has a Field signal output pin.
Pin output and Field relation is shown as follows.
FIELD Signal State
field information
Low
Odd
High
Even
Value of Field signal is determined during DVALID active.
Field signal does not directly reflect input field , but it is a field signal which is forced to toggle at each VSYNC
signal. Therefore, even when Odd Field only or Even Field only signal is input, Field signal also toggles.
MS0319-E-03
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2004 / 11