AK8855 Datasheet, PDF (67/81 Pages) Asahi Kasei Microsystems – NTSC/PAL Digital Video Decoder

[ASAHI KASEI]
Output Control 2 Register (R/W) [Sub Address 0x02]
Register to set polarity of output pin and to set output condition when no input signal is fed.
AK8855
Sub Address 0x02
bit 7
bit 6
OF_OFF NSIGMD
bit 5
DVALACT
0
0
0
bit 4
bit 3
HVACT
CLKINV
Default Value
0
0
bit 2
DVALIDP
0
Default Value: 0x00
bit 1
bit 0
VDP
HDP
0
0
Output Control 2 Register Definition
BIT
Register
Name
R/
W
Definition
bit 0
HDP
HD pin Polarity set bit
R/
W
to set polarity of HD signal.
0: Active Low
1: Active High
R/ to set polarity of VD signal.
bit 1
VDP
VD pin Polarity set bit
W 0: Active Low
1: Active High
bit 2
DVALDP
DVALID pin Polarity set
bit
R/ to set polarity of DVALID signal.
W 0: Active Low
1: Active High
R/ to set polarity of CLKO.
W 0: normal output
bit 3
CLKINV CLK invert set bit
( data should be taken at the rising edge )
1: phase relation between data and clock is
inverted
( data should be taken at the falling edge ).
to output HD & VD in EAV / SAV Interface
bit 4
HVACT
HD/VD action bit
R/ mode.
W no output ( fixed to low )
1 : to output
to output DVALID signal in EAV / SAV Interface
bit 5
DVALACT DVALID action bit
R/ mode.
W 0: no output ( fixed to low )
1: to output
to decide output condition when no signal input
bit 6
NSIGMD
No SiGnal Output MoDe
R/
W
condition is detected.
0 : to output Black level
1 : to output input condition directly as is
( “ Sand-Storm “ condition ).
to turn off the vertical interpolator filter in the
bit 7
OF_OFF OutputFilter_OFF bit
R/ rotated QVGA output operation.
W 0 : with vertical interpolator filter
1 : without vertical interpolator filter
MS0319-E-03
67
2004 / 11