AK8855 Datasheet, PDF (42/81 Pages) Asahi Kasei Microsystems – NTSC/PAL Digital Video Decoder

[ASAHI KASEI]
AK8855
(2) Interface by HD / VD / DVALID
Synchronization is made by HD / VD.
DVALID signal which becomes active during active Video interval, is used.
Since Even / Odd Field recognition is possible by HD / VD signal, interlace information is known.
In the AK8855, data is output by DVALID signal which becomes active during active Video region.
Relation between DVALID signal and data is shown in the following diagram ( example shown is at 27 MHz
sampling ).
DVALID signal which indicates active video interval, is output at the following timing shown below ( 601 output
case ).
Video Signal
HD
DVALID
CLKO
D[7:0]
Cb0 Y0 Cr0 Y1 Cb1 Y2 Cr1 Y3
Y718 Cr359 Y719
Active Video Start position
( in normal operation, it is at 123th / 133th ( NTSC / PAL ) sampling, counting f rom 0h point )(601 mode )
Timing Diagram is shown below.
CLKO
HD
b
DVALID
a
DATA[7:0]
FF 00 00 SAV Cb0 Y0 Cr0 Y1 Cb1 Y2 Cr1
FF 00 00 EAV
( data FF0000SAV & FF0000EAV are at Rec.656 mode. For other than Rec.656 mode, they are replaced with
10H80H10H80H data )
Mode
[OFORM2:OFRO
M0]
525-Line (VLF-bit = 0)
Number of CLKO count
a
b
CLKO Rate
625-Line (VLF-bit = 1)
Number of CLKO count
a
b
CLKO Rate
QVGA
000
118 640 12.2727MHz 127 640 12.2727MHz
VGA
001
236 1280 24.5454MHz 254 1280 24.5454MHz
CIF
010
130 704
27.0MHz
140 704
13.5MHz
QCIF
011
65 352
6.75MHz
70 352
6.75MHz
Rotated QVGA
100
198 480 12.2727MHz 207 480 12.2727MHz
Rotated CIF
101
150 576 12.2727MHz 159 576 12.2727MHz
601
110
244 1440
27MHz
264 1440
27.0MHz
* note : output data rate of CIF size mode in 525 Line system ( NTSC ) is doubled.
Polarity of CLKO / HD / VD / DVALID is programmable by setting Output Control 2 Register ( R/W ) [ Sub
Address 0x02 ].
Timing diagrams shown at next page and thereafter are for operation at HDP = 0, VDP = 0, DVALDP = 0,
CLKINV = 1 settings.
MS0319-E-03
42
2004 / 11