AK4490EN Datasheet, PDF (57/68 Pages) Asahi Kasei Microsystems – Premium 32-Bit 2ch DAC

[AK4490EN]
Addr Register Name
02H Control 3
R(I2C)/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
DP
0
DCKS DCKB MONO DZFB SELLR SLOW
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
SLOW: Slow Roll-off Filter Enable
0: Sharp roll-off filter (default)
1: Slow roll-off filter
SSLOW bit
0
0
0
0
1
SD bit
0
0
1
1
-
Table 33. Digital Filter Setting
SLOW bit
Mode
0
Sharp roll-off filter
1
Slow roll-off filter
0
Short delay Sharp roll-off filter
1
Short delay Slow roll-off filter
-
Super Slow roll-off filter
(default)
SELLR: The data selection of L channel and R channel
MONO bit
0
0
1
1
Table 34 MONO Mode Output Select
SELLR bit
Lch Out
0
Lch In
1
Rch In
0
Lch In
1
Rch In
Rch Out
Rch In
Lch In
Lch In
Rch In
(default)
DZFB: Inverting Enable of DZF
0: DZF pin goes “H” at Zero Detection (default)
1: DZF pin goes “L” at Zero Detection
Table 35. Zero Detect Function and DZF Pin Output
DZFE DZFB
Data
DZF-pin
0
0
1
-
-
L
H
1
0
1
not zero
Zero detect
not zero
Zero detect
L
H
H
L
MONO: MONO mode Stereo mode select
0: Stereo mode (default)
1: MONO mode
When MONO bit is “1”, MONO mode is enabled.
DCKB: Polarity of DCLK (DSD Only)
0: DSD data is output from DCLK falling edge. (default)
1: DSD data is output from DCLK rising edge.
DCKS: Master Clock Frequency Select at DSD mode (DSD only)
0: 512fs (default)
1: 768fs
DP: DSD/PCM Mode Select
0: PCM Mode (default)
1: DSD Mode
When DP bit is changed, the AK4490EN should be reset by RSTN bit.
015013666-E-01
- 57 -
2015/12