AK4490EN Datasheet, PDF (48/68 Pages) Asahi Kasei Microsystems – Premium 32-Bit 2ch DAC

[AK4490EN]
■ Synchronize Function
The AK4490EN has a function that resets the internal counter to synchronize with the external clock edge
(LRCK) in a range of 3/256fs. Clock synchronize function becomes valid if SYNCE bit is set to “1” during
operation in PCM mode or EXDF mode and input data of both L and R channels are “0” for 8129 times
continuously or RSTN bit is “1”. In PCM mode, the internal counter is synchronized with a falling edged of
LRCK (rising edge of LRCK in I2C mode), and it is synchronized with a falling edge of WCK in EXDF
mode. In this case, the analog output has the same voltage as VCML/R. Figure 26 shows a synchronizing
sequence when the input data is “0” for 8192 times continuously. Figure 27 shows a synchronizing
sequence by RSTN bit.
(1) Synchronization by continuous “0” data input for 8192 times
If the input data is “0” for 8192 times continuously, or if the data becomes “0” for 8192 times continuously
by attenuation, the DZFL/DZFR pin goes to “H” and the synchronize function becomes valid. The
synchronize function is enabled only when both L and R channels data are “0” for 8192 times
continuously. Figure 26 shows a synchronizing sequence when the input data is “0” for 8192 times
continuously.
D/A In
(Digital)
SMUTE
ATT_Level
Attenuation
GD
AOUT
(1)
(1)
-
GD
GD
(4)
DZF pin
Internal Counter
Reset
Internal
Data Reset
(2)
8192/fs
SYNC
Operation (2)
4~5/fs (3)
(2)
8192/fs
SYNC
Operation (2)
(5)
Note 34.
(1) ATT_DATA  ATT transition time. For example, this time is 7395LRCK cycles (1020/fs) at
ATT_DATA=255 in Normal Speed Mode.
(2) When both L and R channels data are “0” for 8192 times continuously, DZFL/R pins become “H” and
the synchronize function is valid.
(3) Internal data is fixed to “0” forcibly for 4 to 5/fs when internal counter is reset.
(4) A click noise may occur when the internal counter is reset. This noise is output even if a “0” data is
input. Mute the analog output externally if this click noise affects the system performance.
(5) When the internal clock and external clock are in synchronization, the internal counter is not reset
even if the synchronize function is valid.
Figure 26. Synchronizing Sequence by Continuous “0” Data Input for 8192 Times
015013666-E-01
- 48 -
2015/12