AK4490EN Datasheet, PDF (20/68 Pages) Asahi Kasei Microsystems – Premium 32-Bit 2ch DAC

[AK4490EN]
■ Switching Characteristics
(Ta=25C; AVDD=DVDD=3.0  3.6, TVDD=1.6V  DVDD, VREFHL/R=VDDL/R=4.75  5.25V)
Parameter
Symbol Min.
Typ. Max.
Master Clock Timing
Frequency
fCLK
7.7
49.152
Duty Cycle
dCLK
40
60
LRCK Frequency
1152fs, 512fs or 768fs
256fs or 384fs
128fs or 192fs
64fs
64fs
Duty Cycle
(Note 23)
fsn
30
54
fsd
54
108
fsq
108
216
fsoc
384
fssd
768
Duty
45
55
PCM Audio Interface Timing
BICK Period
1152fs, 512fs or 768fs
tBCK 1/128fsn
256fs or 384fs
tBCK 1/64fsd
128fs or 192fs
tBCK 1/64fsq
64fs
tBCK 1/64fso
64fs
tBCK 1/64fsh
BICK Pulse Width Low
tBCKL
9
BICK Pulse Width High
tBCKH
9
BICK “” to LRCK Edge (Note 24)
tBLR
5
LRCK Edge to BICK “” (Note 24)
tLRB
5
SDATA Hold Time
tSDH
5
SDATA Setup Time
tSDS
5
External Digital Filter Mode
BICK Period
tB
27
BCK Pulse Width Low
tBL
10
BCK Pulse Width High
tBH
10
BCK “” to WCK Edge
tBW
5
WCK Edge to BCK “”
tWB
5
WCK Pulse Width Low
tWCK
54
WCK Pulse Width High
tWCH
54
DATA Hold Time
tDH
5
DATA Setup Time
tDS
5
DSD Audio Interface Timing (64 mode,
DSDSEL 1-0 bits = “00”)
DCLK Period
DCLK Pulse Width Low
DCLK Pulse Width High
DCLK Edge to DSDL/R
(Note 25)
tDCK
1/64fs
tDCKL
160
tDCKH
160
tDDD
20
20
DSD Audio Interface Timing (128 mode,
DSDSEL 1-0 bits = “01”)
DCLK Period
tDCK
1/128fs
DCLK Pulse Width Low
tDCKL
80
DCLK Pulse Width High
tDCKH
80
DCLK Edge to DSDL/R (Note 25)
tDDD
10
10
Unit
MHz
%
kHz
kHz
kHz
kHz
kHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
015013666-E-01
- 20 -
2015/12