AK4490EN Datasheet, PDF (28/68 Pages) Asahi Kasei Microsystems – Premium 32-Bit 2ch DAC

[AK4490EN]
(1) Parallel Mode (PSN pin = “H”)
1. Manual Setting Mode (ACKS pin = “L”)
The MCLK frequency corresponding to each sampling speed should be provided externally (Table 3).
DFS1-0 bit is fixed to “00”. In this mode, only normal speed mode are available.
Table 3. System Clock Example (Manual Setting Mode @Parallel Mode) (N/A: Not available)
LRCK
MCLK (MHz)
BICK
fs
128fs 192fs 256fs 384fs 512fs 768fs 1024fs 1152fs
64fs
32.0kHz N/A N/A 8.1920 12.2880 16.3840 24.5760 32.7680 36.8640 2.0480MHz
44.1kHz N/A N/A 11.2896 16.9344 22.5792 33.8688 N/A
N/A 2.8224MHz
48.0kHz N/A N/A 12.2880 18.4320 24.5760 36.8640 N/A
N/A 3.0720MHz
2. Auto Setting Mode (ACKS pin = “H”)
In auto setting mode, MCLK frequency and sampling frequency are detected automatically (Table 4).
MCLK of corresponded frequency to each sampling speed mode should be input externally. (Table 5)
Table 4. Sampling Speed (Auto Setting Mode @Parallel Mode)
MCLK
Sampling Speed
1152fs
512/256fs 768/384fs
Normal (fs32kHz)
Normal
256fs
384fs
Double
128fs
192fs
Quad
64fs
96fs
Oct
32fs
48fs
Hex
LRCK
Fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
384kHz
768kHz
Table 5. System Clock Example (Auto Setting Mode @Parallel Mode) (N/A: Not available)
32fs
48fs
MCLK (MHz)
64fs
96fs
128fs
192fs
256fs
384fs
512fs
768fs 1024fs
N/A
N/A
N/A
N/A
N/A
N/A
8.192 12.288 16.384 24.576 32.768
N/A
N/A
N/A
N/A
N/A
N/A
11.2896 16.9344 22.5792 33.8688 N/A
N/A
N/A
N/A
N/A
N/A
N/A
12.288 18.432 24.576 36.864 N/A
N/A
N/A
N/A
N/A
N/A
N/A
22.5792 33.8688
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
24.576 36.864
N/A
N/A
N/A
N/A
N/A
N/A
N/A 22.5792 33.8688
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A 24.576 36.864
N/A
N/A
N/A
N/A
N/A
N/A
N/A
24.576 36.864 N/A
N/A
N/A
N/A
N/A
N/A
N/A
24.576 36.864
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1152fs
36.864
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Sampling
Speed
Normal
Double
Quad
Quad
Oct
Hex
When MCLK= 256fs/384fs, auto setting mode supports sampling rate of 32kHz~96kHz. However, the DR
and S/N performances will degrade approximately 3dB as compared to when MCLK= 512fs/768fs when
the sampling rate is 32kHz~48kHz (Table 6).
Table 6. Relationship of MCLK Frequency and DR, S/N Performance (fs = 44.1kHz)
ACKS pin
MCLK
DR,S/N
L
256fs/384fs/512fs/768fs
120dB
H
256fs/384fs
117dB
H
512fs/768fs
120dB
015013666-E-01
- 28 -
2015/12