AK4490EN Datasheet, PDF (21/68 Pages) Asahi Kasei Microsystems – Premium 32-Bit 2ch DAC

[AK4490EN]
DSD Audio Interface Timing (256 mode,
DSDSEL 1-0 bit = “10”)
DCLK Period
tDCK
1/256fs
ns
DCLK Pulse Width Low
tDCKL
40
ns
DCLK Pulse Width High
tDCKH
40
ns
DCLK Edge to DSDL/R (Note 25)
tDDD
5
5
ns
Control Interface Timing
CCLK Period
tCCK
200
ns
CCLK Pulse Width Low
tCCKL
80
ns
Pulse Width High
tCCKH
80
ns
CDTI Setup Time
tCDS
50
ns
CDTI Hold Time
tCDH
50
ns
CSN High Time
tCSW
150
ns
CSN “” to CCLK “”
tCSS
50
ns
CCLK “” to CSN “”
tCSH
50
Control Interface Timing (I²C Bus mode):
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 26)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed by Input
Filter
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tSP
-
1.3
0.6
1.3
0.6
0.6
0
0.1
-
-
0.6
0
Capacitive load on bus
Cb
-
ns
400 kHz
-
s
-
s
-
s
-
s
-
s
-
s
-
s
0.3
s
0.3
s
-
s
50
ns
400 pF
Reset Timing
PDN Pulse Width
(Note 27)
tPD
150
ns
Note 23. When the 1152fs, 512fs or 768fs /256fs or 384fs /128fs or 192fs are switched, the AK4490EN
should be reset by the PDN pin or RSTN bit.
Note 24. BICK rising edge must not occur at the same time as LRCK edge.
Note 25. DSD data transmitting device must meet this time.
Note 26. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note 27. The AK4490EN can be reset by bringing the PDN pin to “L”.
When the AK8157A is used for MCLK, Minimum Pulse Width is specified as below.
Parameter
Master Clock Timing
Frequency1 (CKSEL= “00”)
Frequency2 (CKSEL= “01”)
Frequency3 (CKSEL= “10” / “11”)
Minimum Pulse Width
Symbol
fCLK
fCLK
fCLK
tCLKH / tCLKL
min
typ
9.155
16.384
22.5792
24.576
max
Unit
MHz
MHz
MHz
ns
015013666-E-01
- 21 -
2015/12