AK4490EN Datasheet, PDF (32/68 Pages) Asahi Kasei Microsystems – Premium 32-Bit 2ch DAC

[AK4490EN]
[2] DSD Mode
The AK4490EN has a DSD playback function. The external clocks, which are required in DSD mode, are
MCLK and DCLK. MCLK should be synchronized with DCLK but the phase is not critical. The frequency
of MCLK is set by DCKS bit.
The AK4490EN is automatically placed in reset state when MCLK is stopped during a normal operation
(PDN pin =“H”), and the analog output becomes Hi-z state. However, the external clock (DCLK) should
not be stopped. When DCLK is not supplied, the AK4490EN may not be able to operate properly because
of an over current since it has a dynamic logic circuit internally. The PDN pin should be set to “L” when
stopping the DCLK. When the reset is released (PDN pin = “L” → “H”), the AK4490EN is in power-down
state until MCLK and DCLK are input.
DCKS bit
0
1
Table 14. System Clock (DSD Mode)
MCLK Frequency DCLK Frequency
512fs
64fs/128fs/256fs
768fs
64fs/128fs/256fs
(default)
The AK4490EN supports DSD data stream of 2.8224MHz (64fs), 5.6448MHz (128fs) and 11.2896MHz
(256fs). The data sampling speed is selected by DSDSEL1-0 bits.
Table 15. DSD Sampling Speed Control
DSDSEL1 DSDSEL0 DSD data stream
0
0
2.8224MHz (default)
0
1
5.6448MHz
1
0
11.2896MHz
1
1
Reserved
The AK4490EN has a Volume bypass function for play backing DSD signal. Two modes are selectable by
DSDD bit. When setting DSDD bit = “1”, the output volume control function is not available.
Table 16. DSD Play Back Mode Control
DSDD
Mode
0
Normal Path (default)
1
Volume Bypass
When DSDD bit = “1”, filter characteristic can be switched between 50kHz and 100kHz by DSDF bit.
DSDD bit
0
0
1
1
Table 17. DSD Filter Select
DSDF bit
Cut Off Filter
0
50kHz
1
Reserved
0
50kHz
1
150kHz
(default)
015013666-E-01
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2015/12