AK4490EN Datasheet, PDF (27/68 Pages) Asahi Kasei Microsystems – Premium 32-Bit 2ch DAC

[AK4490EN]
9. Functional Descriptions
■ D/A Conversion Mode
In serial mode, the AK4490EN can perform D/A conversion for either PCM data or DSD data. The DP bit
controls PCM/DSD mode. When DSD mode, DSD data can be input from DCLK, DSDL and DSDR pins.
When PCM mode, PCM data can be input from BICK, LRCK and SDATA pins. When PCM/DSD mode is
changed by DP bit, the AK4490EN should be reset by RSTN bit. It takes about 2/fs to 3/fs to change the
mode. In parallel mode, the AK4490EN performs for only PCM data.
Table 1. PCM/DSD Mode Control
DP bit Interface
0
PCM
1
DSD
When DP bit= “0”, an internal digital filter or external digital filter can be selected. When using an external
digital filter (EX DF I/F mode), data is input to each MCLK, BCK, WCK, DINL and DINR pin. EXDF bit
controls the modes. When switching internal and external digital filters, the AK4490EN must be reset by
RSTN bit. A Digital filter switching takes 2~3k/fs.
Table 2. Digital Filter Control (DP bit = “0”)
EXDF bit Interface
0
PCM
1
EX DF I/F
■ System Clock
[1] PCM Mode
The external clocks, which are required to operate the AK4490EN, are MCLK, BICK and LRCK. MCLK
should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital
interpolation filter and the delta-sigma modulator. There are two modes for MCLK frequency setting:
Manual Setting Mode and Auto Setting Mode. In manual setting mode, MCLK frequency is set
automatically (Table 3,Table 9). In auto setting mode, sampling speed and MCLK frequency are detected
automatically (Table 4, Table 10) and then the initial master clock is set to the appropriate frequency
(Table 5, Table 11). When the reset is released (PDN pin = “”), the AK4490EN is in auto setting mode.
The AK4490EN is automatically placed in reset state when MCLK and LRCK are stopped during a normal
operation (PDN pin =“H”), and the analog output becomes Hi-z state. When MCLK and LRCK are input
again, the AK4490EN exits reset state and starts operation. After exiting system reset (PDN pin
=“L”→“H”) at power-up and other situations, the AK4490EN is in power-down mode until MCLK and
LRCK are supplied.
The MCLK frequency corresponding to each sampling speed should be provided externally (Table 3,
Table 4, Table 9, Table 10).
015013666-E-01
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2015/12