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AK4490EN Datasheet, PDF (52/68 Pages) Asahi Kasei Microsystems – Premium 32-Bit 2ch DAC | |||
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[AK4490EN]
(2)-2. READ Operations
Set the R/W bit = â1â for the READ operation of the AK4490EN. After transmission of data, the master can
read the next addressâs data by generating an acknowledge instead of terminating the write cycle after
the receipt of the first data word. After receiving each data packet the internal address counter is
incremented by one, and the next data is automatically taken into the next address. If the address
exceeds â09Hâ prior to generating stop condition, the address counter will âroll overâ to â00Hâ and the data
of â00Hâ will be read out.
The AK4490EN supports two basic read operations: Current Address Read and Random Address Read.
(2)-2-1. Current Address Read
The AK4490EN has an internal address counter that maintains the address of the last accessed word
incremented by one. Therefore, if the last access (either a read or write) were to address ânâ, the next
CURRENT READ operation would access data from the address ân+1â. After receipt of the slave address
with R/W bit â1â, the AK4490EN generates an acknowledge, transmits 1-byte of data to the address set by
the internal address counter and increments the internal address counter by 1. If the master does not
generate an acknowledge but generates a stop condition instead, the AK4490EN ceases the
transmission.
SDA
S
T
A
R/W= â1â
R
T
S
Slave
Address
Data(n)
Data(n+1) Data(n+2)
A
A
A
A
C
C
C
C
K
K
K
K
S
T
O
P
Data(n+x) P
A
A
C
C
K
K
Figure 33. Current Address Read
(2)-2-2. Random Address Read
The random read operation allows the master to access any memory location at random. Prior to issuing
the slave address with the R/W bit â1â, the master must first perform a âdummyâ write operation. The
master issues a start request, a slave address (R/W bit = â0â) and then the register address to read. After
the register address is acknowledged, the master immediately reissues the start request and the slave
address with the R/W bit â1â. The AK4490EN then generates an acknowledge, 1 byte of data and
increments the internal address counter by 1. If the master does not generate an acknowledge but
generates a stop condition instead, the AK4490EN ceases the transmission.
SDA
S
T
A
R
T
S
Slave
Address
R/W= â0â
Sub
Address(n)
A
C
K
S
T
A
R
T
S
Slave
Address
A
C
K
R/W= â1â
Data(n)
A
C
K
Data(n+1)
A
A
C
C
K
K
S
T
O
P
Data(n+x) P
A
A
C
C
K
K
Figure 34. Random Address Read
015013666-E-01
- 52 -
2015/12
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