AK4490EN Datasheet, PDF (45/68 Pages) Asahi Kasei Microsystems – Premium 32-Bit 2ch DAC

[AK4490EN]
■ Power ON/OFF timing
The AK4490EN is placed in the power-down mode by bringing the PDN pin “L” and the registers are
initialized. The analog outputs are floating (Hi-Z). As some click noise occurs at the edge of the PDN pin
signal, the analog output should be muted externally if the click noise influences system application.
The DAC can be reset by setting RSTN bit to “0”. In this case, registers are not initialized and the
corresponding analog outputs go to VCML/R. As some click noise occurs at the edge of RSTN signal, the
analog output should be muted externally if click noise aversely affect system performance.
Power
PDN pin
(1)
Internal
State
Normal Operation
DAC In
(Digital)
“0”data
DAC Out
(Analog)
(3)
(4)
Clock In
MCLK,LRCK,BICK ⁽⁸⁾
DZFL/DZFR
External
Mute
(6)
Mute ON
GD ⁽²⁾
Reset
“0”data
GD
(4)
(3)
(5)
(8)
(7)
Mute ON
Note 31.
(1) Digital and analog power supply should be powered up at the same time, otherwise power up the
1.8V base power supplies (TVDD) at first, the 3.3V base power supplies secondarily (DVDD,
AVDD) and 5V base power supplies finally (VDDL/R, VREFHL/R). After TVDD, AVDD and DVDD
reach to 90%VDD, the PDN pin should be “L” for 150ns or more.
(2) The analog output corresponding to digital input has group delay (GD).
(3) Analog outputs are floating (Hi-Z) in power-down mode.
(4) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.
(5) MCLK, BICK and LRCK clocks can be stopped in power-down mode (PDN pin= “L”).
(6) Mute the analog output externally if click noise (4) adversely affect system performance
The timing example is shown in this figure.
(7) DZFL/R pins are “L” in the power-down mode (PDN pin = “L”).
(8) Clocks should be input after power supplies are powered up.
Figure 23. Power-down/up Sequence Example
015013666-E-01
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2015/12