AK8157A Datasheet, PDF (4/26 Pages) Asahi Kasei Microsystems – Multiclock Generator for Premium Audio Device

■ Pin Layout
5. Pin Configurations and Functions
4
3
2
1
D
CAD1 VDD2 VSS1 CLKIN
C
VDD3 SDA SCL CAD0
B
VSS2 RSTN LRCK VDD1
A
BCLK
VDD4 VSS3
Top view
MCLK
[AK8157A]
Figure 2. AK8157A Package: 16-pin WLCSP (Top View)
■ Pin Functions
No. Pin Name I/O
Function
A1 MCLK
O Master Clock Output Pin (Internal pull-down pin: 160k)
A2 VSS3
- Ground Pin
A3 VDD4
- Power Supply Pin, 1.7  2.0V
A4 BCLK
O Audio Serial Data Clock Output Pin (Internal pull-down pin: 160k)
B1 VDD1
- Power Supply Pin, 1.7  2.0V
B2 LRCK
O L/R Clock Output Pin (Internal pull-down pin: 160k)
B3 RSTN
Register Reset Control Pin
I
When at “L”, the register of the AK8157A is held in reset.
The AK8157A must always be reset upon power-up.
B4 VSS2
- Ground Pin
C1 CAD0
I Chip Address 0 Pin
C2 SCL
I Control Data Clock Input Pin
C3 SDA
I/O Control Data Input / Output Pin
C4 VDD3
- Power Supply Pin, 1.7  2.0V
D1 CLKIN
I 9.6MHz External Clock Input Pin
D2 VSS1
- Ground Pin
D3 VDD2
- Power Supply Pin, 1.7  2.0V
D4 CAD1
I Chip Address 1 Pin
Note: All input pins must not be allowed to float.
015002776-E-00
-4-
2015/03