AK8157A Datasheet, PDF (15/26 Pages) Asahi Kasei Microsystems – Multiclock Generator for Premium Audio Device

[AK8157A]
(2) Power-up by changing MCK_DIS bit, BCK_DIS bit and LR_DIS bit from “1” to “0”
CLKIN
Output State
SCL/SDA
Power-up Setting
PLL State
MCLK
BCLK
LRCK
Don’t care
Disable
Disable
(2)
Power down
(1)
Power up
“Power on” setting
Power down
Unlocked
Disable state (Hi-Z & Pull-down)
Enable
”Enable” setting
Power up
Locked
Clock is enabled without a glitch
(1) Internal circuits of the AK8157A are switched to power-up state by setting internal registers
(PLL1_PD bit, PLL2_PD bit and VREF_PD bit).
(2) After PLL1_PD bit, PLL2_PD bit and VREF_PD bit are changed, it is recommended to change
MCK_DIS bit, BCK_DIS bit and LR_DIS bit to “0” from “1” with an interval of 1ms or more for
glitch-free outputs of MCLK, BICK and LRCK.
Figure 10. Power-up Sequence Example
015002776-E-00
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2015/03