AK8157A Datasheet, PDF (11/26 Pages) Asahi Kasei Microsystems – Multiclock Generator for Premium Audio Device

[AK8157A]
9. Functional Descriptions
■ System Clock Timing
The AK8157A can generate MCLK, BCLK and LRCK simultaneously from 9.6MHz external input clock. It
requires operating the AK8157A with an audio device such as the AK4490, the AK4495 and so on. MCLK,
BCLK and LRCK phases are synchronized on a falling edge. (Figure 6).
CLKIN
9.6MHz
PLL1 PLL2
ODIV1
ODIV2
ODIV3
MCLK
BCLK
LRCK
Figure 6. System Clock Timing
The MCLK, BCLK and LRCK frequencies corresponding to each sampling speed can be selected by
MDSEL1-0 bits and MCKSEL1-0 bits (Table 1). Normal speed, double speed, quad speed and oct speed
modes are available with the AK8157A.
MDSEL1-0 bits
00
01
10
11
Table 1. Output Clock Configuration
MCKSEL1-0 bits
00
MCLK (MHz)
16.384
BCLK (MHz)
64fs
2.048
01
22.5792 _512fs
2.8224
10 / 11
24.576
3.072
00
16.384
4.096
01
22.5792 _256fs
5.6448
10 / 11
24.576
6.144
00
16.384
8.192
01
22.5792 _128fs
11.2896
10 / 11
24.576
12.288
00
16.384
16.384
01
22.5792 _64fs
22.5792
10 / 11
24.576
24.576
LRCK (kHz)
fs
32
44.1
48
64
88.2
96
128
176.4
192
256
352.8
384
Sampling
Speed
Normal
Double
Quad
Oct
■ System Reset
The AK8157A should be reset once by bringing the RSTN pin = “L” upon power-up. It initializes register
settings of the device.
015002776-E-00
- 11 -
2015/03