AK8157A Datasheet, PDF (20/26 Pages) Asahi Kasei Microsystems – Multiclock Generator for Premium Audio Device

[AK8157A]
■ Register Map
Addr
Register
Name
D7
D6
D5
D4
D3
D2
D1
D0
00H Control 1
LR_DIS BCK_DIS MCK_DIS reserved reserved VREF_PD PLL2_PD PLL1_PD
01H Control 2
reserved reserved MDSEL1 MDSEL0 reserved reserved MCKSEL1 MCKSEL0
Notes:
The AK8157A supports read command in I²C-bus control mode.
Data must not be written into addresses from 02H to 1FH.
The reserved bits defined as “0” must contain a “0” value.
When the RSTN pin goes to “L”, the registers are initialized to their default values.
■ Register Definitions
Addr
00H
Register
Name
Control 1
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
LR_DIS
R/W
1
BCK_DIS MCK_DIS reserved
R/W
R/W
R
1
1
0
reserved VREF_PD PLL2_PD PLL1_PD
R
R/W
R/W
R/W
0
0
0
0
PLL1_PD: PLL1 Power Management
0: Power up (default)
1: Power down
PLL2_PD: PLL2 Power Management
0: Power up (default)
1: Power down
VREF_PD: Internal VREF Power Management
0: Power up (default)
1: Power down
MCK_DIS: MCLK pin Output Clock Control
0: Enable: Clock Output
1: Disable: “L” Output by 160k (typ.) pull-down resistor (default)
BCK_DIS: MCLK pin Output Clock Control
0: Enable: 64fs Clock Output
1: Disable: “L” Output by 160k (typ.) pull-down resistor (default)
LR_DIS: LRCK pin Output Clock Control
0: Enable: fs Clock Output
1: Disable: “L” Output by 160k (typ.) pull-down resistor (default)
015002776-E-00
- 20 -
2015/03