AK8157A Datasheet, PDF (13/26 Pages) Asahi Kasei Microsystems – Multiclock Generator for Premium Audio Device

[AK8157A]
■ Glitch-free Function
The AK8157A has a Glitch-free function. MCLK, BCLK and LRCK output clocks can be switched
enable and disable without a glitch.
■ Frequency Configuration Change Sequence
When outputs frequency of the MCLK, BCLK and LRCK are changed by internal register setting
(MDSEL1-0 bits and MCKSEL1-0 bits), it is recommended to disable output clocks to not output
unstable frequency clock.
CLKIN
Output State
SCL/SDA
Enable
(1)
Disable
”Disable” setting
(3)
Frequency Setting _{Configuration1}
(2)
Configuration2
Frequency changing
PLL State
Locked
Unlock
MCLK
BCLK
LRCK
Disable state (Hi-Z & Pull-down)
Clock is disabled without a glitch
Enable
”Enable” setting
Locked
Clock is enabled without a glitch
(1) MCK_DIS bit, BCK_DIS bit and LR_DIS bit are changed from “0” to “1”.
(2) The output clock frequency configuration can be changed by internal register setting (MDSEL1-0
bits and MCKSEL1-0 bits).
(3) After changing the output clock frequency Configuration2, it is recommended to change
MCK_DIS bit, BCK_DIS bit and LR_DIS bit to “0” from “1” with an interval of 1ms or more. Then
MCLK, BCLK and LRCK can be output without a glitch.
Figure 8. Frequency Configuration Change Sequence Example
015002776-E-00
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2015/03