AK8157A Datasheet, PDF (14/26 Pages) Asahi Kasei Microsystems – Multiclock Generator for Premium Audio Device

[AK8157A]
■ Power-down and Power-up Sequence by Internal Registers
Internal circuits of the AK8157A can be powered down and up by setting registers (PLL1_PD bit,
PLL2_PD bit and VREF_PD bit). It is recommended to disable output clocks to not output unstable
frequency clocks when internal circuits of the AK8157A are powered down and up.
(1) Power-down by changing MCK_DIS bit, BCK_DIS bit and LR_DIS bit from “0” to “1”
CLKIN
Output State
SCL/SDA
Power-down Setting
PLL State
MCLK
BCLK
LRCK
Don’t care
Enable
(1)
Disable
”Disable” setting
Power up
Locked
Power down
“Power down” setting
(2)
Power down
Disable state (Hi-Z & Pull-down)
Clock is disabled without a glitch
(1) MCK_DIS bit, BCK_DIS bit and LR_DIS bit are changed from “0” to “1”.
(2) Internal circuits of the AK8157A are powered down by setting internal registers (PLL1_PD bit,
PLL2_PD bit and VREF_PD bit).
Figure 9. Power-down Sequence Example
015002776-E-00
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2015/03