AK8157A Datasheet, PDF (12/26 Pages) Asahi Kasei Microsystems – Multiclock Generator for Premium Audio Device

[AK8157A]
■ Power-up Timing
Registers of the AK8157A are initialized by bringing the RSTN pin to “L”. The MCLK, BCLK and LRCK
outputs are floating (Hi-Z) and connected to 160k pull-down internally. PLL1, PLL2 and VREF circuits
are power-up.
Registers of the AK8157A are able to write when RSTN pin is change to “H”.
Power
VDD1
VDD2
1.7V
VDD3
VDD4
RSTN
(1)
SCL/SDA
CLKIN
PLL State
MCLK
BCLK
LRCK
Register Initialization
Don’t care
Register Setting Available
Frequency Setting
Output Clock Enable Setting
(2)
Unlocked
Locked
Disable state (Hi-Z & Pull-down)
(3)
Clock is enabled without a glitch
(1) VDD1-4 power supply should be powered up at the same time by bringing the RSTN pin to “L”.
Registers of the AK8157A are initialized by bringing the RSTN pin to “L”.
After VDD1-3 reach 1.7V, the RSTN pin should be changed from “L” to “H” with an interval of
200s or more.
(2) When the RSTN pin is “H”, the output clock frequency configuration can be selected by internal
register setting (MDSEL1-0 bits and MCKSEL1-0 bits). After setting the output clock frequency
configuration, MCK_DIS bit, BCK_DIS bit and LR_DIS bit are recommended to change from “1” to
“0” with an interval of 1ms or more to output MCLK, BCLK and LRCK clocks without a glitch.
(3) The MCLK, BCLK and LRCK outputs are floating (Hi-Z) and connected to 160k pull-down
internally.
Figure 7. Power-up Timing Example
015002776-E-00
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2015/03