AK4392 Datasheet, PDF (36/41 Pages) Asahi Kasei Microsystems – High Performance 120dB Premium 32-Bit DAC

Digital Ground
System
Controller
Analog Ground
1 DVDD
2 PDN
3 BICK/DCLK
4 SDATA/DSDL
5 LRCK/DSDR/WCK
6 SMUTE/CSN
7 DFS0/CAD0
8 DEM0/CCLK
9 DEM1/CDTI
10 DIF0/CAD1
11 DIF1/DZFL
[AK4392]
AOUTLN 33
VSS2 32
VDDL 31
VREFHL 30
VREFLL 29
NC
28
VREFLR 27
VREFHR 26
VDDR 25
VSS1 24
AOUTRN 23
Figure 18. Ground Layout
1. Grounding and Power Supply Decoupling
To minimize coupling by digital noise, decoupling capacitors should be connected to AVDD, VDDL/R and DVDD
respectively. AVDD and VDDL/R are supplied from analog supply in system and DVDD is supplied from digital supply in
system. Power lines of AVDD, VDDL/R and DVDD should be distributed separately from the point with low impedance of
regulator etc. The power up sequence between AVDD, VDDL/R and DVDD is not critical. VSS1-4 must be
connected to the same analog ground plane. Decoupling capacitors for high frequency should be placed as near as
possible to the supply pin.
2. Voltage Reference
The differential voltage between VREFHL/R and VREFLL/R sets the analog output range. The VREFHL/R pin is
normally connected to AVDD, and the VREFLL/R pin is normally connected to VSS1/2/3. VREFHL/R and VREFLL/R
should be connected with a 0.1µF ceramic capacitor as near as possible to the pin to eliminate the effects of high frequency
noise. No load current may be drawn from VCML/R pin. All signals, especially clocks, should be kept away from the
VREFHL/R and VREFLL/R pins in order to avoid unwanted noise coupling into the AK4392.
3. Analog Outputs
The analog outputs are full differential outputs and 2.8Vpp (typ, VREFHL/R − VREFLL/R = 5V) centered around
AVDD/2. The differential outputs are summed externally, V_AOUT = (AOUT+) − (AOUT−) between AOUT+ and AOUT−.
If the summing gain is 1, the output range is 5.6Vpp (typ, VREFHL/R − VREFLL/R = 5V). The bias voltage of the external
summing circuit is supplied externally. The input data format is 2's complement. The output voltage (V_AOUT) is a positive
full scale for 7FFFFFH (@24bit) and a negative full scale for 800000H (@24bit). The ideal V_AOUT is 0V for
000000H(@24bit).
The internal switched-capacitor filters attenuate the noise generated by the delta-sigma modulator beyond the audio
passband. Figure 19 shows an example of external LPF circuit summing the differential outputs by an op-amp.
Figure 20 shows an example of differential outputs and LPF circuit example by three op-amps.
MS1045-E-02
- 36 -
2009/04