AK4392 Datasheet, PDF (28/41 Pages) Asahi Kasei Microsystems – High Performance 120dB Premium 32-Bit DAC

[AK4392]
■ Reset Function
(1) RESET by RSTN bit = “0”
When the RSTN bit = “0”, the AK4392’s digital block is powered down, but the internal register values are not initialized.
In this time, the analog outputs go to VCML/R voltage and DZFL/DZFR pins are “H”. Figure 14 shows an example of
reset by RSTN bit.
RSTN bit
In ternal
RSTN bit
In ternal
Stat e
D/A In
(Dig ital )
D/A Out
(Ana log )
DZF
3~4/fs (5)
2~3/fs (5)
Normal Operation
(1)
GD
D igital Block
P
d
“0 ” data
(3) (2)
Normal O peration
GD (1)
(3)
2/ fs(4)
(6)
Notes:
(1) The analog output corresponding to digital input has group delay (GD).
(2) Analog outputs settle to VCOM voltage.
(3) Small pop noise occurs at the edges(“↑ ↓”) of the internal timing of RSTN bit. This noise is output even if “0”
data is input.
(4) The DZF pins change to “H” when the RSTN bit becomes “0”, and return to “L” at 2/fs after RSTN bit becomes
“1”.
(5) There is a delay, 3~4/fs from RSTN bit “0” to the internal RSTN bit “0”, and 2~3/fs from RSTN bit “1” to the
internal RSTN bit “1”.
(6) Mute the analog output externally if click noise (3) and Hi-Z (2) adversely affect system performance
Figure 14. Reset Sequence Example 1
MS1045-E-02
- 28 -
2009/04