AK4392 Datasheet, PDF (29/41 Pages) Asahi Kasei Microsystems – High Performance 120dB Premium 32-Bit DAC

[AK4392]
(2) RESET by MCLK or LRCK/WCK Stop
The AK4392 is automatically placed in reset state when MCLK or LRCK is stopped during PDM mode (RSTN pin
=“H”), and the analog outputs are floating (Hi-Z). When MCLK and LRCK are input again, the AK4392 exits reset state
and starts the operation. Zero detect function is disable when MCLK or LRCK is stopped. In DSD mode the AK4392 is in
reset state when MCLK is stopped, and it is in reset state when MCLK and WCK are stopped in external digital filter
mode.
AVDD pin
DVDD pin
RSTB pin
(1)
In ternal
Stat e
Power-down
Normal O peration
D/A In
(Dig ital )
Power-down
D/A Out
(Analog)
Clock In
MCLK, BICK, LRCK
Hi-Z
(4)
GD (2)
Digital Circuit P ower-down
Normal Operation
(3)
(4)
(5)
(4)
(5)
MCLK, BICK, LRCK Stop
GD (2)
Ex terna l
MUTE
(6)
(6)
(6)
Notes:
(1) After AVDD and DVDD are powered-up, the PDN pin should be “L” for 150ns.
(2) The analog output corresponding to digital input has group delay (GD).
(3) The digital data can be stopped. Click noise after MCLK, BICK and LRCK are input again can be reduced by
inputting “0” data during this period.
(4) Click noise occurs within 3 ~ 4LRCK cycles from the riding edge (“↑”) of the PDN pin or MCLK inputs. This
noise occurs even when “0” data is input.
(5) Clocks (MCLK, BICK, LRCK) can be stopped in the reset state (MCLK or LRCK is stopped).
(6) Mute the analog output externally if click noise (4) influences system applications. The timing example is shown
in this figure.
Figure 15. Reset Sequence Example 2
MS1045-E-02
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2009/04