AK4392 Datasheet, PDF (19/41 Pages) Asahi Kasei Microsystems – High Performance 120dB Premium 32-Bit DAC

[AK4392]
■ Audio Interface Format
[1] PCM Mode
Data is shifted in via the SDATA pin using BICK and LRCK inputs. Eight data formats are supported and selected by the
DIF2-0 pins (Parallel control mode) or DIF2-0 bits (Serial control mode) as shown in Table 7. In all formats the serial data
is MSB-first, 2's compliment format and is latched on the rising edge of BICK. Mode 2 can be used for 20-bit and 16-bit
MSB justified formats by zeroing the unused LSBs. Settings should be made by DIF2-0 pins in parallel mode and DIF2-0
bits in serial mode.
Mode
0
1
2
3
4
5
6
7
DIF2
0
0
0
0
1
1
1
1
DIF1
0
0
1
1
0
0
1
1
DIF0
Input Format
0
16bit LSB justified
1
20bit LSB justified
0
24bit MSB justified
1
24bit I²S Compatible
0
24bit LSB justified
1
32bit LSB justified
0
32bit MSB justified
1
32bit I²S Compatible
Table 7. Audio Interface Format
BICK
≥ 32fs
≥ 48fs
≥ 48fs
≥ 48fs
≥ 48fs
≥ 64fs
≥64fs
≥ 64fs
Figure
Figure 1
Figure 2
Figure 3
Figure 4
Figure 2
Figure 5
Figure 6
Figure 7
(default)
LRCK
BICK
(32fs)
SDATA
Mode 0
BICK
(64fs)
SDATA
Mode 0
01
10 11 12 13 14 15 0 1
15 14
01
6 5 4 3 2 1 0 15 14
14 15 16 17
31 0 1
Don’t care
15 14
0 Don’t care
15:MSB, 0:LSB
Lch Data
Figure 1. Mode 0 Timing
10 11 12 13 14 15 0 1
6 5 4 3 2 1 0 15 14
14 15 16 17
31 0 1
15 14
0
Rch Data
LRCK
BICK
(64fs)
SDATA
Mode 1
SDATA
Mode 4
01
8 9 10 11 12
31 0 1
8 9 10 11 12
Don’t care
19
0 Don’t care
19
19:MSB, 0:LSB
Don’t care 23 22 21 20 19
0 Don’t care 23 22 21 20 19
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 2. Mode 1/4 Timing
31 0 1
0
0
MS1045-E-02
- 19 -
2009/04