AK4392 Datasheet, PDF (13/41 Pages) Asahi Kasei Microsystems – High Performance 120dB Premium 32-Bit DAC

[AK4392]
Note 15. When the 1152fs, 512fs or 768fs /256fs or 384fs /128fs or 192fs are switched, the AK4392 should be reset by the
PDN pin or RSTN bit.
Note 16. BICK rising edge must not occur at the same time as LRCK edge.
Note 17. DSD data transmitting device must meet this time.
Note 18. The AK4392 can be reset by bringing the PDN pin “L” to “H” upon power-up.
■ Timing Diagram
1/fCLK
MCLK
tCLKH
tCLKL
1/fs
LRCK
BICK
WCK
tBCK
tBCKH
tBCKL
1/fs
BCK
tB
tBH
tBL
VIH
VIL
dCLK=tCLKH x fCLK, tCLKL x fCLK
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
Clock Timing
MS1045-E-02
- 13 -
2009/04