AK4392 Datasheet, PDF (17/41 Pages) Asahi Kasei Microsystems – High Performance 120dB Premium 32-Bit DAC

[AK4392]
OPERATION OVERVIEW
■ D/A Conversion Mode
In serial mode, the AK4392 can perform D/A conversion for either PCM data or DSD data. The D/P bit controls
PCM/DSD mode. When DSD mode, DSD data can be input from DCLK, DSDL and DSDR pins. When PCM mode,
PCM data can be input from BICK, LRCK and SDATA pins. When PCM/DSD mode is changed by D/P bit, the AK4392
should be reset by RSTN bit. It takes about 2/fs to 3/fs to change the mode. In parallel mode, the AK4392 performs for
only PCM data.
DP bit Interface
0
PCM
1
DSD
Table 1. PCM/DSD Mode Control
When DP bit= “0”, an internal digital filter or external digital filter can be selected. When using an external digital filter
(EX DF I/F mode), data is input to each MCLK, BCK, WCK, DINL and DINR pin. EXDF bit controls the modes. When
switching internal and external digital filters, the AK4392 must be reset by RSTN bit. A Digital filter switching takes
2~3k/fs.
Ex DF bit Interface
0
PCM
1
EX DF I/F
Table 2. Digital Filter Control (DP bit = “0”)
■ System Clock
[1] PCM Mode
The external clocks, which are required to operate the AK4392, are MCLK, BICK and LRCK. MCLK should be
synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the
delta-sigma modulator. Sampling speed and MCLK frequency are detected automatically and then the initial master clock
is set to the appropriate frequency (Table 3). When external clocks are changed, the AK4392 should be reset by the PDN
pin or RSTN bit.
The AK4392 is automatically placed in reset state when MCLK and LRCK are stopped during a normal operation (PDN
pin =“H”), and the analog output becomes Hi-Z. When MCLK and LRCK are input again, the AK4392 exit reset state and
starts the operation. After exiting system reset (PDN pin =“L”→“H”) at power-up and other situations, the AK4392 is in
power-down mode until MCLK and LRCK are supplied.
The MCLK frequency corresponding to each sampling speed should be provided (Table 4).
MCLK
Mode
1152fs
Normal
512fs
768fs
Normal
256fs
384fs
Double
128fs
192fs
Quad
Table 3. Sampling Speed
Sampling Rate
30kHz~32kHz
30kHz~54kHz
30kHz~108kHz
108kHz~216kHz
MS1045-E-02
- 17 -
2009/04