AK4392 Datasheet, PDF (35/41 Pages) Asahi Kasei Microsystems – High Performance 120dB Premium 32-Bit DAC

[AK4392]
SYSTEM DESIGN
Figure 17 shows the system connection diagram. Figure 19, Figure 20 and Figure 21 show the analog output circuit
examples. The evaluation board (AKD4392) demonstrates the optimum layout, power supply arrangements and
measurement results.
Analog5.0V
Digital 5.0V
Reset & PD
6 4fs
Audio Data
fs
Micro -
Contr olle r
1 0u
+
0.1u
1 DVD D
2 PDN
3 BIC K
4 SDATA
5 LRCK
6 CSN
7 CAD 0
8 CCLK
9 CDTI
10 CAD 1
11 DZFL
10u
++
0.1 u
+
1 0u
Lch
Lch
LPF Mute
Lch Out
AK4392EQ
To p View
AOUTLN 33
VSS2 32
0 .1u
VDDL 31
VREFHL 30
VREFLL 29 ^0.1u
NC 28
VREFLR 27
0 .1u
VR EFHR 26
VDDR 25
0 .1u
VSS1 24
AOUTRN 23
10 u
+
+
10u
10 u
+
+
10 u
Rch
Rch
+
10u
LPF
Mute _{Rch Out}
D ig ital
Analog
Gd
+ _{Electrolytic Capacitor}
Ceramic Capacitor
Notes:
- Chip Address = “00”. BICK = 64fs, LRCK = fs
- Power lines of AVDD and DVDD should be distributed separately from the point with low impedance of regulator etc.
- VSS1-4 must be connected to the same analog ground plane.
- When AOUT drives a capacitive load, some resistance should be connected in series between AOUT and the
capacitive load.
- All input pins except pull-down/pull-up pins should not be allowed to float.
Figure 17. Typical Connection Diagram (AVDD=VDDL/R=5V, DVDD=5V, Serial control mode)
MS1045-E-02
- 35 -
2009/04