AK4392 Datasheet, PDF (18/41 Pages) Asahi Kasei Microsystems – High Performance 120dB Premium 32-Bit DAC

[AK4392]
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
MCLK (MHz)
128fs
192fs
256fs
384fs
512fs
768fs
N/A
N/A
8.1920 12.2880 16.3840 24.5760
N/A
N/A
11.2896 16.9344 22.5792 33.8688
N/A
N/A
12.2880 18.4320 24.5760 36.8640
N/A
N/A
22.5792 33.8688
N/A
N/A
N/A
N/A
24.5760 36.8640
N/A
N/A
22.5792 33.8688
N/A
N/A
N/A
N/A
24.5760 36.8640
N/A
N/A
N/A
N/A
Table 4. System Clock Example (Parallel Control Mode) (N/A: Not available)
1152fs
36.8640
N/A
N/A
N/A
N/A
N/A
N/A
MCLK= 256fs/384fs supports sampling rate of 30kHz~108kHz (Table 5). But, when the sampling rate is 30kHz~54kHz,
DR and S/N will degrade by approximately 3dB as compared to when MCLK= 512fs/768fs.
MCLK
DR,S/N
256fs/384fs
117dB
512fs/768fs
120dB
Table 5. Relationship between MCLK frequency and DR, S/N (fs= 44.1kHz)
[2] DSD Mode
The external clocks, which are required to operate the AK4392, are MCLK and DCLK. MCLK should be synchronized
with DCLK but the phase is not critical. The frequency of MCLK is set by DCKS bit.
The AK4392 is automatically placed in reset state when MCLK is stopped during a normal operation (PDN pin =“H”),
and the analog output becomes Hi-Z. After exiting system reset (PDN pin =“L”→“H”) at power-up and other situations,
the AK4392 is in power-down mode until MCLK is supplied.
DCKS bit
0
1
MCLK Frequency DCLK Frequency
512fs
64fs
768fs
64fs
Table 6. System Clock (DSD Mode)
(default)
MS1045-E-02
- 18 -
2009/04